1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_HAVE_ACPI_TABLES
5 uses CONFIG_HAVE_ACPI_RESUME
6 uses CONFIG_USE_FALLBACK_IMAGE
7 uses CONFIG_HAVE_FALLBACK_BOOT
8 uses CONFIG_HAVE_HARD_RESET
9 uses CONFIG_IRQ_SLOT_COUNT
10 uses CONFIG_HAVE_OPTION_TABLE
12 uses CONFIG_MAX_PHYSICAL_CPUS
13 uses CONFIG_LOGICAL_CPUS
16 uses CONFIG_FALLBACK_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_IMAGE_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_SECTION_OFFSET
22 uses CONFIG_ROM_PAYLOAD
23 uses CONFIG_ROM_PAYLOAD_START
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_PAYLOAD_SIZE
28 uses CONFIG_XIP_ROM_SIZE
29 uses CONFIG_XIP_ROM_BASE
30 uses CONFIG_STACK_SIZE
32 uses CONFIG_USE_OPTION_TABLE
33 uses CONFIG_LB_CKS_RANGE_START
34 uses CONFIG_LB_CKS_RANGE_END
35 uses CONFIG_LB_CKS_LOC
36 uses CONFIG_MAINBOARD_PART_NUMBER
37 uses CONFIG_MAINBOARD_VENDOR
39 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
40 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
41 uses COREBOOT_EXTRA_VERSION
43 uses CONFIG_TTYS0_BAUD
44 uses CONFIG_TTYS0_BASE
46 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
47 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
48 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
49 uses CONFIG_CONSOLE_SERIAL8250
50 uses CONFIG_HAVE_INIT_TIMER
53 uses CONFIG_CROSS_COMPILE
57 uses CONFIG_CONSOLE_VGA
58 uses CONFIG_PCI_ROM_RUN
59 uses CONFIG_HW_MEM_HOLE_SIZEK
60 uses CONFIG_HT_CHAIN_UNITID_BASE
61 uses CONFIG_HT_CHAIN_END_UNITID_BASE
62 uses CONFIG_SB_HT_CHAIN_ON_BUS0
64 uses CONFIG_USE_DCACHE_RAM
65 uses CONFIG_DCACHE_RAM_BASE
66 uses CONFIG_DCACHE_RAM_SIZE
68 uses CONFIG_USE_PRINTK_IN_CAR
70 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
77 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
79 default CONFIG_ROM_SIZE=524288
82 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
84 #default CONFIG_FALLBACK_SIZE=131072
86 default CONFIG_FALLBACK_SIZE=0x40000
89 ## Build code for the fallback boot
91 default CONFIG_HAVE_FALLBACK_BOOT=1
94 ## Build code to reset the motherboard from coreboot
96 default CONFIG_HAVE_HARD_RESET=1
99 ## Build code to export a programmable irq routing table
101 default CONFIG_HAVE_PIRQ_TABLE=1
102 default CONFIG_IRQ_SLOT_COUNT=11
105 ## Build code to export an x86 MP table
106 ## Useful for specifying IRQ routing values
108 default CONFIG_HAVE_MP_TABLE=1
111 ## Build code to export a CMOS option table
113 default CONFIG_HAVE_OPTION_TABLE=1
116 ## Move the default coreboot cmos range off of AMD RTC registers
118 default CONFIG_LB_CKS_RANGE_START=49
119 default CONFIG_LB_CKS_RANGE_END=122
120 default CONFIG_LB_CKS_LOC=123
123 ## Build code for SMP support
124 ## Only worry about 2 micro processors
127 default CONFIG_MAX_CPUS=4
128 default CONFIG_MAX_PHYSICAL_CPUS=2
129 default CONFIG_LOGICAL_CPUS=1
132 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
135 #default CONFIG_CONSOLE_VGA=1
136 #default CONFIG_PCI_ROM_RUN=1
139 default CONFIG_HT_CHAIN_UNITID_BASE=0x6
142 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
144 #make the SB HT chain on bus 0
145 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
148 ## enable CACHE_AS_RAM specifics
150 default CONFIG_USE_DCACHE_RAM=1
151 default CONFIG_DCACHE_RAM_BASE=0xcf000
152 default CONFIG_DCACHE_RAM_SIZE=0x1000
153 default CONFIG_USE_INIT=0
156 ## Build code to setup a generic IOAPIC
158 default CONFIG_IOAPIC=1
161 ## Clean up the motherboard id strings
163 default CONFIG_MAINBOARD_PART_NUMBER="blast"
164 default CONFIG_MAINBOARD_VENDOR="Broadcom"
165 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
166 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
170 ### coreboot layout values
173 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
174 default CONFIG_ROM_IMAGE_SIZE = 65536
177 ## Use a small 8K stack
179 default CONFIG_STACK_SIZE=0x2000
182 ## Use a small 16K heap
184 default CONFIG_HEAP_SIZE=0x4000
187 ## Only use the option table in a normal image
189 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
192 ## Coreboot C code runs at this location in RAM
194 default CONFIG_RAMBASE=0x00004000
197 ## Load the payload from the ROM
199 default CONFIG_ROM_PAYLOAD = 1
202 ### Defaults of options that you may want to override in the target config file
206 ## The default compiler
208 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
209 default CONFIG_HOSTCC="gcc"
212 ## Disable the gdb stub by default
214 default CONFIG_GDB_STUB=0
216 default CONFIG_USE_PRINTK_IN_CAR=1
219 ## The Serial Console
222 # To Enable the Serial Console
223 default CONFIG_CONSOLE_SERIAL8250=1
225 ## Select the serial console baud rate
226 default CONFIG_TTYS0_BAUD=115200
227 #default CONFIG_TTYS0_BAUD=57600
228 #default CONFIG_TTYS0_BAUD=38400
229 #default CONFIG_TTYS0_BAUD=19200
230 #default CONFIG_TTYS0_BAUD=9600
231 #default CONFIG_TTYS0_BAUD=4800
232 #default CONFIG_TTYS0_BAUD=2400
233 #default CONFIG_TTYS0_BAUD=1200
235 # Select the serial console base port
236 default CONFIG_TTYS0_BASE=0x3f8
238 # Select the serial protocol
239 # This defaults to 8 data bits, 1 stop bit, and no parity
240 default CONFIG_TTYS0_LCS=0x3
243 ### Select the coreboot loglevel
245 ## EMERG 1 system is unusable
246 ## ALERT 2 action must be taken immediately
247 ## CRIT 3 critical conditions
248 ## ERR 4 error conditions
249 ## WARNING 5 warning conditions
250 ## NOTICE 6 normal but significant condition
251 ## INFO 7 informational
252 ## CONFIG_DEBUG 8 debug-level messages
253 ## SPEW 9 Way too many details
255 ## Request this level of debugging output
256 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
257 ## At a maximum only compile in this level of debugging
258 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
261 ## Select power on after power fail setting
262 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
269 default CONFIG_CBFS=0