1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_GENERATE_ACPI_TABLES
4 uses CONFIG_HAVE_ACPI_RESUME
5 uses CONFIG_USE_FALLBACK_IMAGE
6 uses CONFIG_HAVE_FALLBACK_BOOT
7 uses CONFIG_HAVE_HARD_RESET
8 uses CONFIG_IRQ_SLOT_COUNT
9 uses CONFIG_HAVE_OPTION_TABLE
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
15 uses CONFIG_FALLBACK_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_IMAGE_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_SECTION_OFFSET
21 uses CONFIG_ROM_PAYLOAD
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
40 uses CONFIG_TTYS0_BAUD
41 uses CONFIG_TTYS0_BASE
43 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
44 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
45 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
47 uses CONFIG_HAVE_INIT_TIMER
50 uses CONFIG_CROSS_COMPILE
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses CONFIG_HW_MEM_HOLE_SIZEK
57 uses CONFIG_HT_CHAIN_UNITID_BASE
58 uses CONFIG_HT_CHAIN_END_UNITID_BASE
59 uses CONFIG_SB_HT_CHAIN_ON_BUS0
61 uses CONFIG_USE_DCACHE_RAM
62 uses CONFIG_DCACHE_RAM_BASE
63 uses CONFIG_DCACHE_RAM_SIZE
65 uses CONFIG_USE_PRINTK_IN_CAR
67 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
74 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
76 default CONFIG_ROM_SIZE=524288
79 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
81 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
84 ## Build code for the fallback boot
86 default CONFIG_HAVE_FALLBACK_BOOT=1
89 ## Build code to reset the motherboard from coreboot
91 default CONFIG_HAVE_HARD_RESET=1
94 ## Build code to export a programmable irq routing table
96 default CONFIG_GENERATE_PIRQ_TABLE=1
97 default CONFIG_IRQ_SLOT_COUNT=11
100 ## Build code to export an x86 MP table
101 ## Useful for specifying IRQ routing values
103 default CONFIG_GENERATE_MP_TABLE=1
106 ## Build code to export a CMOS option table
108 default CONFIG_HAVE_OPTION_TABLE=1
111 ## Move the default coreboot cmos range off of AMD RTC registers
113 default CONFIG_LB_CKS_RANGE_START=49
114 default CONFIG_LB_CKS_RANGE_END=122
115 default CONFIG_LB_CKS_LOC=123
118 ## Build code for SMP support
119 ## Only worry about 2 micro processors
122 default CONFIG_MAX_CPUS=4
123 default CONFIG_MAX_PHYSICAL_CPUS=2
124 default CONFIG_LOGICAL_CPUS=1
127 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
130 #default CONFIG_CONSOLE_VGA=1
131 #default CONFIG_PCI_ROM_RUN=1
134 default CONFIG_HT_CHAIN_UNITID_BASE=0x6
137 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
139 #make the SB HT chain on bus 0
140 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
143 ## enable CACHE_AS_RAM specifics
145 default CONFIG_USE_DCACHE_RAM=1
146 default CONFIG_DCACHE_RAM_BASE=0xcf000
147 default CONFIG_DCACHE_RAM_SIZE=0x1000
148 default CONFIG_USE_INIT=0
151 ## Build code to setup a generic IOAPIC
153 default CONFIG_IOAPIC=1
156 ## Clean up the motherboard id strings
158 default CONFIG_MAINBOARD_PART_NUMBER="blast"
159 default CONFIG_MAINBOARD_VENDOR="Broadcom"
160 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
161 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
165 ### coreboot layout values
168 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
169 default CONFIG_ROM_IMAGE_SIZE = 65536
172 ## Use a small 8K stack
174 default CONFIG_STACK_SIZE=0x2000
177 ## Use a small 16K heap
179 default CONFIG_HEAP_SIZE=0x4000
182 ## Only use the option table in a normal image
184 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
187 ## Coreboot C code runs at this location in RAM
189 default CONFIG_RAMBASE=0x00004000
192 ## Load the payload from the ROM
194 default CONFIG_ROM_PAYLOAD = 1
197 ### Defaults of options that you may want to override in the target config file
201 ## The default compiler
203 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
207 ## Disable the gdb stub by default
209 default CONFIG_GDB_STUB=0
211 default CONFIG_USE_PRINTK_IN_CAR=1
214 ## The Serial Console
217 # To Enable the Serial Console
218 default CONFIG_CONSOLE_SERIAL8250=1
220 ## Select the serial console baud rate
221 default CONFIG_TTYS0_BAUD=115200
222 #default CONFIG_TTYS0_BAUD=57600
223 #default CONFIG_TTYS0_BAUD=38400
224 #default CONFIG_TTYS0_BAUD=19200
225 #default CONFIG_TTYS0_BAUD=9600
226 #default CONFIG_TTYS0_BAUD=4800
227 #default CONFIG_TTYS0_BAUD=2400
228 #default CONFIG_TTYS0_BAUD=1200
230 # Select the serial console base port
231 default CONFIG_TTYS0_BASE=0x3f8
233 # Select the serial protocol
234 # This defaults to 8 data bits, 1 stop bit, and no parity
235 default CONFIG_TTYS0_LCS=0x3
238 ### Select the coreboot loglevel
240 ## EMERG 1 system is unusable
241 ## ALERT 2 action must be taken immediately
242 ## CRIT 3 critical conditions
243 ## ERR 4 error conditions
244 ## WARNING 5 warning conditions
245 ## NOTICE 6 normal but significant condition
246 ## INFO 7 informational
247 ## CONFIG_DEBUG 8 debug-level messages
248 ## SPEW 9 Way too many details
250 ## Request this level of debugging output
251 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
252 ## At a maximum only compile in this level of debugging
253 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
256 ## Select power on after power fail setting
257 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"