2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
22 default CONFIG_XIP_ROM_SIZE = 128 * 1024
23 include /config/nofailovercalculation.lb
24 default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
28 if CONFIG_GENERATE_PIRQ_TABLE
32 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
33 action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
35 makerule ./failover.inc
36 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
37 action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
40 # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
41 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
42 action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
45 # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
46 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
47 action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
49 mainboardinit cpu/x86/16bit/entry16.inc
50 mainboardinit cpu/x86/32bit/entry32.inc
51 ldscript /cpu/x86/16bit/entry16.lds
52 ldscript /cpu/x86/32bit/entry32.lds
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/reset16.inc
55 ldscript /cpu/x86/16bit/reset16.lds
57 mainboardinit cpu/x86/32bit/reset32.inc
58 ldscript /cpu/x86/32bit/reset32.lds
60 mainboardinit arch/i386/lib/cpu_reset.inc
61 mainboardinit arch/i386/lib/id.inc
62 ldscript /arch/i386/lib/id.lds
63 if CONFIG_USE_FALLBACK_IMAGE
64 ldscript /arch/i386/lib/failover.lds
65 mainboardinit ./failover.inc
67 mainboardinit cpu/x86/fpu/enable_fpu.inc
68 mainboardinit ./auto.inc
69 mainboardinit cpu/x86/mmx/disable_mmx.inc
74 chip northbridge/intel/i440bx # Northbridge
75 device apic_cluster 0 on # APIC cluster
76 chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
77 device apic 0 on end # APIC
80 device pci_domain 0 on # PCI domain
81 device pci 0.0 on end # Host bridge
82 device pci 1.0 on end # PCI/AGP bridge
83 chip southbridge/intel/i82371eb # Southbridge
84 device pci 7.0 on # ISA bridge
85 chip superio/smsc/smscsuperio # Super I/O
86 device pnp 3f0.0 on # Floppy
91 device pnp 3f0.3 on # Parallel port
95 device pnp 3f0.4 on # COM1
99 device pnp 3f0.5 on # COM2 / IR
103 device pnp 3f0.7 on # PS/2 keyboard / mouse
106 irq 0x70 = 1 # PS/2 keyboard interrupt
107 irq 0x72 = 12 # PS/2 mouse interrupt
109 device pnp 3f0.8 on # Aux I/O
113 device pci 7.1 on end # IDE
114 device pci 7.2 on end # USB
115 device pci 7.3 on end # ACPI
116 register "ide0_enable" = "1"
117 register "ide1_enable" = "1"
118 register "ide_legacy_enable" = "1"
119 # Enable UDMA/33 for higher speed if your IDE device(s) support it.
120 register "ide0_drive0_udma33_enable" = "0"
121 register "ide0_drive1_udma33_enable" = "0"
122 register "ide1_drive0_udma33_enable" = "0"
123 register "ide1_drive1_udma33_enable" = "0"