2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <arch/ioapic.h>
24 #include <device/pci.h>
28 static void *smp_write_config_table(void *v)
30 struct mp_config_table *mc;
32 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
34 mptable_init(mc, "P2B-DS ", LAPIC_ADDR);
36 smp_write_processors(mc);
38 /* Bus: Bus ID Type */
39 smp_write_bus(mc, 0, "PCI ");
40 smp_write_bus(mc, 1, "ISA ");
42 /* I/O APICs: APIC ID Version State Address */
43 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
48 dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
50 res = find_resource(dev, PCI_BASE_ADDRESS_0);
52 smp_write_ioapic(mc, 3, 0x20, res->base);
54 dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
56 res = find_resource(dev, PCI_BASE_ADDRESS_0);
58 smp_write_ioapic(mc, 4, 0x20, res->base);
60 dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
62 res = find_resource(dev, PCI_BASE_ADDRESS_0);
64 smp_write_ioapic(mc, 5, 0x20, res->base);
66 dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
68 res = find_resource(dev, PCI_BASE_ADDRESS_0);
70 smp_write_ioapic(mc, 8, 0x20, res->base);
74 mptable_add_isa_interrupts(mc, 0x1, 0x2, 0);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
77 0x0, 0x13, 0x2, 0x13);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
79 0x0, 0x18, 0x2, 0x13);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
81 0x0, 0x30, 0x2, 0x10);
83 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
84 smp_write_lintsrc(mc, mp_ExtINT,
85 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0,
87 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
88 0x1, 0x0, MP_APIC_ALL, 0x1);
90 /* There is no extension information... */
92 /* Compute the checksums */
94 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
95 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
96 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
97 mc, smp_next_mpe_entry(mc));
98 return smp_next_mpe_entry(mc);
101 unsigned long write_smp_table(unsigned long addr)
104 v = smp_write_floating_table(addr);
105 return (unsigned long)smp_write_config_table(v);