src/mainboard/asus/mew-vm/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16
  17 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
  18 #object reset.o
  19
  20 ##
  21 ## Romcc output
  22 ##
  23 makerule ./failover.E
  24         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  25         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  26 end
  27
  28 makerule ./failover.inc
  29         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  30         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  31 end
  32
  33 makerule ./auto.E
  34         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  35         action  "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  36 end
  37 makerule ./auto.inc
  38         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  39         action  "../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  40 end
  41
  42 ##
  43 ## Build our 16 bit and 32 bit coreboot entry code
  44 ##
  45 mainboardinit cpu/x86/16bit/entry16.inc
  46 mainboardinit cpu/x86/32bit/entry32.inc
  47 ldscript /cpu/x86/16bit/entry16.lds
  48 ldscript /cpu/x86/32bit/entry32.lds
  49
  50 ##
  51 ## Build our reset vector (This is where coreboot is entered)
  52 ##
  53 if CONFIG_USE_FALLBACK_IMAGE
  54         mainboardinit cpu/x86/16bit/reset16.inc
  55         ldscript /cpu/x86/16bit/reset16.lds
  56 else
  57         mainboardinit cpu/x86/32bit/reset32.inc
  58         ldscript /cpu/x86/32bit/reset32.lds
  59 end
  60
  61 ### Should this be in the northbridge code?
  62 mainboardinit arch/i386/lib/cpu_reset.inc
  63
  64 ##
  65 ## Include an id string (For safe flashing)
  66 ##
  67 mainboardinit arch/i386/lib/id.inc
  68 ldscript /arch/i386/lib/id.lds
  69
  70 ###
  71 ### This is the early phase of coreboot startup
  72 ### Things are delicate and we test to see if we should
  73 ### failover to another image.
  74 ###
  75 if CONFIG_USE_FALLBACK_IMAGE
  76         ldscript /arch/i386/lib/failover.lds
  77         mainboardinit ./failover.inc
  78 end
  79
  80 ###
  81 ### O.k. We aren't just an intermediary anymore!
  82 ###
  83
  84 ##
  85 ## Setup RAM
  86 ##
  87 mainboardinit cpu/x86/fpu/enable_fpu.inc
  88 mainboardinit cpu/x86/mmx/enable_mmx.inc
  89 mainboardinit ./auto.inc
  90 mainboardinit cpu/x86/mmx/disable_mmx.inc
  91
  92 ##
  93 ## Include the secondary Configuration files
  94 ##
  95 dir /pc80
  96 config chip.h
  97
  98 chip northbridge/intel/i82810
  99         device pci_domain 0 on
 100                 device pci 0.0 on end # Host bridge
 101                 device pci 1.0 on # Onboard Video
 102                         #chip drivers/pci/onboard
 103                         #       device pci 1.0 on end
 104                         #       register "rom_address" = "0xfff80000"
 105                         #end
 106                 end
 107                 chip southbridge/intel/i82801xx # Southbridge
 108                         register "ide0_enable" = "1"
 109                         register "ide1_enable" = "1"
 110
 111                         device pci 1e.0 on # PCI Bridge
 112                                 #chip drivers/pci/onboard
 113                                 #       device pci 1.0 on end
 114                                 #       register "rom_address" = "0xfff80000"
 115                                 #end
 116                         end
 117                         device pci 1f.0 on  # ISA/LPC? Bridge
 118                                 chip superio/smsc/lpc47b272
 119                                         device pnp 2e.0 off # Floppy
 120                                                 io 0x60 = 0x3f0
 121                                                 irq 0x70 = 6
 122                                                 drq 0x74 = 2
 123                                         end
 124                                         device pnp 2e.3 off # Parallel Port
 125                                                 io 0x60 = 0x378
 126                                                 irq 0x70 = 7
 127                                         end
 128                                         device pnp 2e.4 on # Com1
 129                                                 io 0x60 = 0x3f8
 130                                                 irq 0x70 = 4
 131                                         end
 132                                         device pnp 2e.5 off # Com2
 133                                                 io 0x60 = 0x2f8
 134                                                 irq 0x70 = 3
 135                                         end
 136                                         device pnp 2e.7 on # Keyboard
 137                                                 io 0x60 = 0x60
 138                                                 io 0x62 = 0x64
 139                                                 irq 0x70 = 1 # Keyboard interrupt
 140                                                 irq 0x72 = 12 # Mouse interrupt
 141                                         end
 142                                         device pnp 2e.a off end # ACPI
 143                                 end
 144                         end
 145                         device pci 1f.1 on end # IDE
 146                         device pci 1f.2 on end # USB
 147                         device pci 1f.3 on end # SMBus
 148                         device pci 1f.5 off end # AC'97, no header on MEW-VM
 149                         device pci 1f.6 off end # AC'97 Modem (MC'97)
 150                 end
 151         end
 152         chip cpu/intel/socket_PGA370
 153         end
 154 end
 155