Please bear with me - another rename checkin. This qualifies as trivial, no
[coreboot.git] / src / mainboard / asus / mew-am / auto.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19  */
20
21 #define ASSEMBLY 1
22
23 #include <stdint.h>
24 #include <stdlib.h>
25 #include <device/pci_def.h>
26 #include <arch/io.h>
27 #include <device/pnp_def.h>
28 #include <arch/romcc_io.h>
29 #include <arch/hlt.h>
30 #include "pc80/serial.c"
31 #include "arch/i386/lib/console.c"
32 #include "ram/ramtest.c"
33 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
34 #include "northbridge/intel/i82810/raminit.h"
35 #include "mainboard/asus/mew-vm/debug.c"        /* FIXME */
36 #include "pc80/udelay_io.c"
37 #include "lib/delay.c"
38 #include "cpu/x86/mtrr/earlymtrr.c"
39 #include "cpu/x86/bist.h"
40 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
41
42 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
43
44 static inline int spd_read_byte(unsigned int device, unsigned int address)
45 {
46         return smbus_read_byte(device, address);
47 }
48
49 #include "northbridge/intel/i82810/raminit.c"
50 /* #include "northbridge/intel/i82810/debug.c" */
51 #include "sdram/generic_sdram.c"
52
53 static void main(unsigned long bist)
54 {
55         static const struct mem_controller memctrl[] = {
56                 {
57                         .d0 = PCI_DEV(0, 0, 0),
58                         .channel0 = {0x50, 0x51},
59                 }
60         };
61
62         if (bist == 0)
63                 early_mtrr_init();
64
65         smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
66         uart_init();
67         console_init();
68         report_bist_failure(bist);
69         enable_smbus();
70         /* dump_spd_registers(&memctrl[0]); */
71         sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
72         /* ram_check(0, 640 * 1024); */
73 }