src/mainboard/asus/m5a99x-evo/rd890_cfg.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include "NbPlatform.h"
  21 #include "rd890_cfg.h"
  22 #include "northbridge/amd/cimx/rd890/chip.h"
  23 #include "nbInitializer.h"
  24 #include <string.h>
  25 #include <arch/ioapic.h>
  26
  27 #ifndef __PRE_RAM__
  28 #include <device/device.h>
  29 extern void set_pcie_reset(void *config);
  30 extern void set_pcie_dereset(void *config);
  31
  32 /**
  33  * Platform dependent configuration at ramstage
  34  */
  35 static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
  36 {
  37         u16 i;
  38         PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
  39         //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
  40         struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
  41         DEFAULT_PLATFORM_CONFIG(platform_config);
  42
  43         /* update the platform depentent configuration by devicetree */
  44         rd890_info  = nb_dev->chip_info;
  45         platform_config.PortEnableMap = rd890_info->port_enable;
  46         if (rd890_info->gpp1_configuration == 0) {
  47                 platform_config.Gpp1Config = GFX_CONFIG_AAAA;
  48         } else if (rd890_info->gpp1_configuration == 1) {
  49                 platform_config.Gpp1Config = GFX_CONFIG_AABB;
  50         }
  51         if (rd890_info->gpp2_configuration == 0) {
  52                 platform_config.Gpp2Config = GFX_CONFIG_AAAA;
  53         } else if (rd890_info->gpp2_configuration == 1) {
  54                 platform_config.Gpp2Config = GFX_CONFIG_AABB;
  55         }
  56         platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
  57
  58         if (platform_config.Gpp1Config != 0) {
  59                 pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
  60         }
  61         if (platform_config.Gpp2Config != 0) {
  62                 pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
  63         }
  64         if (platform_config.Gpp3aConfig != 0) {
  65                 pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
  66         }
  67
  68         pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
  69         for (i = 0; i <= MAX_CORE_ID; i++) {
  70                 NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
  71                 NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
  72         }
  73         for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
  74                 NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
  75         }
  76
  77         for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
  78                 if ((platform_config.PortEnableMap & (1 << i)) != 0) {
  79                         pPcieConfig->PortConfiguration[i].PortPresent = ON;
  80                         if ((platform_config.PortGen1Map & (1 << i)) != 0) {
  81                                 pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
  82                         }
  83                         if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
  84                                 u16 j;
  85                                 pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
  86                                 /* Set Hotplug descriptor info */
  87                                 for (j = 0; j < 8; j++) {
  88                                         u32 PortDescriptor;
  89                                         PortDescriptor = platform_config.PortHotplugDescriptors[j];
  90                                         if ((PortDescriptor & 0xF) == j) {
  91                                                 pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
  92                                                 pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
  93                                                 break;
  94                                         }
  95                                 }
  96                         }
  97                 }
  98         }
  99 }
 100 #endif // __PRE_RAM__
 101
 102 /**
 103  * @brief Entry point of Northbridge CIMx callout/CallBack
 104  *
 105  * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
 106  *
 107  * @param[in] u32 func               Northbridge CIMx CallBackId
 108  * @param[in] u32 data               Northbridge Input Data.
 109  * @param[in] AMD_NB_CONFIG *config  Northbridge configuration structure pointer.
 110  *
 111  */
 112 static u32 rd890_callout_entry(u32 func, u32 data, void *config)
 113 {
 114         u32 ret = 0;
 115 #ifndef __PRE_RAM__
 116         device_t nb_dev = (device_t)data;
 117 #endif
 118         AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
 119
 120         switch (func) {
 121                 case PHCB_AmdPortTrainingCompleted:
 122                         break;
 123
 124                 case PHCB_AmdPortResetDeassert:
 125 #ifndef __PRE_RAM__
 126                         set_pcie_dereset(config);
 127 #endif
 128                         break;
 129
 130                 case PHCB_AmdPortResetAssert:
 131 #ifndef __PRE_RAM__
 132                         set_pcie_reset(config);
 133 #endif
 134                         break;
 135
 136                 case PHCB_AmdPortResetSupported:
 137                         break;
 138                 case PHCB_AmdGeneratePciReset:
 139                         break;
 140                 case PHCB_AmdGetExclusionTable:
 141                         break;
 142                 case PHCB_AmdAllocateBuffer:
 143                         break;
 144                 case PHCB_AmdUpdateApicInterruptMapping:
 145                         break;
 146                 case PHCB_AmdFreeBuffer:
 147                         break;
 148                 case PHCB_AmdLocateBuffer:
 149                         break;
 150                 case PHCB_AmdReportEvent:
 151                         break;
 152                 case PHCB_AmdPcieAsmpInfo:
 153                         break;
 154
 155                 case CB_AmdSetNbPorConfig:
 156                         break;
 157                 case CB_AmdSetHtConfig:
 158                         /*TODO: different HT path and deempasis for each NB */
 159                         nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
 160
 161                         break;
 162                 case CB_AmdSetPcieEarlyConfig:
 163 #ifndef __PRE_RAM__
 164                         nb_platform_config(nb_dev, nbConfigPtr);
 165 #endif
 166                         break;
 167
 168                 case CB_AmdSetEarlyPostConfig:
 169                         break;
 170
 171                 case CB_AmdSetMidPostConfig:
 172                         nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
 173 #ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
 174                         /* SBIOS must alloc 16K memory for IOMMU MMIO */
 175                         UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
 176                         LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
 177                                         AccessWidth32,
 178                                         &MmcfgBarAddress,
 179                                         nbConfigPtr);
 180                         MmcfgBarAddress &= ~0xf;
 181                         if (MmcfgBarAddress != 0) {
 182                                 nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
 183                         }
 184                         nbConfigPtr->IommuBaseAddress = 0; //disable iommu
 185 #endif
 186                         break;
 187
 188                 case CB_AmdSetLatePostConfig:
 189                         break;
 190
 191                 case CB_AmdSetRecoveryConfig:
 192                         break;
 193         }
 194
 195         return ret;
 196 }
 197
 198
 199 /**
 200  * @brief North Bridge CIMx configuration
 201  *
 202  * should be called before exeucte CIMx function.
 203  * this function will be called in romstage and ramstage.
 204  */
 205 void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
 206 {
 207         u16 i = 0;
 208         PCI_ADDR PciAddress;
 209         u32 val, sbNode, sbLink;
 210
 211         if (!pConfig) {
 212                 return;
 213         }
 214
 215         memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
 216         for (i = 0; i < MAX_NB_COUNT; i++) {
 217                 pConfig->Northbridges[i].pNbConfig      = &nbConfig[i];
 218                 pConfig->Northbridges[i].pHtConfig      = &htConfig[i];
 219                 pConfig->Northbridges[i].pPcieConfig    = &pcieConfig[i];
 220                 pConfig->Northbridges[i].ConfigPtr      = &pConfig;
 221         }
 222
 223         /* Initialize all NB structures */
 224         AmdInitializer(pConfig);
 225
 226         pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 227         //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 228         pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
 229         pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
 230
 231         /*
 232          * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
 233          * Always 0:0:0 on single NB platform.
 234          */
 235         pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
 236
 237         /* Set HT path to NB by SbNode and SbLink */
 238         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
 239         LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
 240         sbNode = (val >> 8) & 0x07;
 241         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
 242         LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
 243         sbLink = (val >> 8) & 0x07; //assum ganged
 244         pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
 245         pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
 246         //TODO: other NBs
 247
 248 #ifndef __PRE_RAM__
 249         /* If temporrary MMIO enable set up CPU MMIO */
 250         for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
 251                 UINT32  MmioBase;
 252                 UINT32  LinkId;
 253                 UINT32  SubLinkId;
 254                 MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
 255                 if (MmioBase != 0) {
 256                         LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
 257                         SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
 258                         /* Set Limit */
 259                         LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
 260                                         AccessWidth32,
 261                                         0x0,
 262                                         ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
 263                                         &(pConfig->Northbridges[i]));
 264                         /* Set Base */
 265                         LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
 266                                         AccessWidth32,
 267                                         0x0,
 268                                         (MmioBase << 12) | 0x3,
 269                                         &(pConfig->Northbridges[i]));
 270                 }
 271         }
 272 #endif
 273 }
 274