2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include "NbPlatform.h"
22 #include "rd890_cfg.h"
23 #include "northbridge/amd/cimx/rd890/chip.h"
24 #include "nbInitializer.h"
25 #include <arch/ioapic.h>
28 #include <device/device.h>
29 extern void set_pcie_reset(void *config);
30 extern void set_pcie_dereset(void *config);
33 * Platform dependent configuration at ramstage
35 static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
38 PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
39 //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
40 struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
41 DEFAULT_PLATFORM_CONFIG(platform_config);
43 /* update the platform depentent configuration by devicetree */
44 rd890_info = nb_dev->chip_info;
45 platform_config.PortEnableMap = rd890_info->port_enable;
46 if (rd890_info->gpp1_configuration == 0) {
47 platform_config.Gpp1Config = GFX_CONFIG_AAAA;
48 } else if (rd890_info->gpp1_configuration == 1) {
49 platform_config.Gpp1Config = GFX_CONFIG_AABB;
51 if (rd890_info->gpp2_configuration == 0) {
52 platform_config.Gpp2Config = GFX_CONFIG_AAAA;
53 } else if (rd890_info->gpp2_configuration == 1) {
54 platform_config.Gpp2Config = GFX_CONFIG_AABB;
56 platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
58 if (platform_config.Gpp1Config != 0) {
59 pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
61 if (platform_config.Gpp2Config != 0) {
62 pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
64 if (platform_config.Gpp3aConfig != 0) {
65 pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
68 pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
69 for (i = 0; i <= MAX_CORE_ID; i++) {
70 NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
71 NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
73 for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
74 NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
77 for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
78 if ((platform_config.PortEnableMap & (1 << i)) != 0) {
79 pPcieConfig->PortConfiguration[i].PortPresent = ON;
80 if ((platform_config.PortGen1Map & (1 << i)) != 0) {
81 pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
83 if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
85 pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
86 /* Set Hotplug descriptor info */
87 for (j = 0; j < 8; j++) {
89 PortDescriptor = platform_config.PortHotplugDescriptors[j];
90 if ((PortDescriptor & 0xF) == j) {
91 pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3;
92 pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1;
100 #endif // __PRE_RAM__
103 * @brief Entry point of Northbridge CIMx callout/CallBack
105 * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
107 * @param[in] u32 func Northbridge CIMx CallBackId
108 * @param[in] u32 data Northbridge Input Data.
109 * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer.
112 static u32 rd890_callout_entry(u32 func, u32 data, void *config)
116 device_t nb_dev = (device_t)data;
118 AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
121 case PHCB_AmdPortTrainingCompleted:
124 case PHCB_AmdPortResetDeassert:
126 set_pcie_dereset(config);
130 case PHCB_AmdPortResetAssert:
132 set_pcie_reset(config);
136 case PHCB_AmdPortResetSupported:
138 case PHCB_AmdGeneratePciReset:
140 case PHCB_AmdGetExclusionTable:
142 case PHCB_AmdAllocateBuffer:
144 case PHCB_AmdUpdateApicInterruptMapping:
146 case PHCB_AmdFreeBuffer:
148 case PHCB_AmdLocateBuffer:
150 case PHCB_AmdReportEvent:
152 case PHCB_AmdPcieAsmpInfo:
155 case CB_AmdSetNbPorConfig:
157 case CB_AmdSetHtConfig:
158 /*TODO: different HT path and deempasis for each NB */
159 nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
162 case CB_AmdSetPcieEarlyConfig:
164 nb_platform_config(nb_dev, nbConfigPtr);
168 case CB_AmdSetEarlyPostConfig:
171 case CB_AmdSetMidPostConfig:
172 nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
173 #ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
174 /* SBIOS must alloc 16K memory for IOMMU MMIO */
175 UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress
176 LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
180 MmcfgBarAddress &= ~0xf;
181 if (MmcfgBarAddress != 0) {
182 nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
184 nbConfigPtr->IommuBaseAddress = 0; //disable iommu
188 case CB_AmdSetLatePostConfig:
191 case CB_AmdSetRecoveryConfig:
200 * @brief North Bridge CIMx configuration
202 * should be called before exeucte CIMx function.
203 * this function will be called in romstage and ramstage.
205 void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
209 u32 val, sbNode, sbLink;
215 memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
216 for (i = 0; i < MAX_NB_COUNT; i++) {
217 pConfig->Northbridges[i].pNbConfig = &nbConfig[i];
218 pConfig->Northbridges[i].pHtConfig = &htConfig[i];
219 pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i];
220 pConfig->Northbridges[i].ConfigPtr = &pConfig;
223 /* Initialize all NB structures */
224 AmdInitializer(pConfig);
226 pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
227 //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
228 pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
229 pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
232 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
233 * Always 0:0:0 on single NB platform.
235 pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
237 /* Set HT path to NB by SbNode and SbLink */
238 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
239 LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
240 sbNode = (val >> 8) & 0x07;
241 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
242 LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
243 sbLink = (val >> 8) & 0x07; //assum ganged
244 pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
245 pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
249 /* If temporrary MMIO enable set up CPU MMIO */
250 for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
254 MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
256 LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
257 SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
259 LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
262 ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
263 &(pConfig->Northbridges[i]));
265 LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
268 (MmioBase << 12) | 0x3,
269 &(pConfig->Northbridges[i]));