2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef _M5A88_V_CFG_H_
22 #define _M5A88_V_CFG_H_
30 #define BIOS_SIZE_1M 0
31 #define BIOS_SIZE_2M 1
32 #define BIOS_SIZE_4M 3
33 #define BIOS_SIZE_8M 7
35 /* In SB800, default ROM size is 1M Bytes, if your platform ROM
36 * bigger than 1M you have to set the ROM size outside CIMx module and
37 * before AGESA module get call.
39 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
40 #define BIOS_SIZE BIOS_SIZE_1M
41 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
42 #define BIOS_SIZE BIOS_SIZE_2M
43 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
44 #define BIOS_SIZE BIOS_SIZE_4M
45 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
46 #define BIOS_SIZE BIOS_SIZE_8M
50 * @def SPREAD_SPECTRUM
52 * 0 - Disable Spread Spectrum function
53 * 1 - Enable Spread Spectrum function
55 #define SPREAD_SPECTRUM 0
67 * @brief bit[0-6] used to control USB
70 * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
71 * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
72 * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
73 * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
74 * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
75 * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
76 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
78 #define USB_CONFIG 0x7F
82 * @breif bit[0-4] used for PCI Slots Clock Control,
85 * PCI SLOT 0 define at BIT0
86 * PCI SLOT 1 define at BIT1
87 * PCI SLOT 2 define at BIT2
88 * PCI SLOT 3 define at BIT3
89 * PCI SLOT 4 define at BIT4
91 #define PCI_CLOCK_CTRL 0x1F
94 * @def SATA_CONTROLLER
95 * @breif INCHIP Sata Controller
97 #define SATA_CONTROLLER CIMX_OPTION_ENABLED
101 * @breif INCHIP Sata Controller Mode
102 * NOTE: DO NOT ALLOW SATA & IDE use same mode
104 #define SATA_MODE NATIVE_IDE_MODE
107 * @breif INCHIP Sata IDE Controller Mode
109 #define IDE_LEGACY_MODE 0
110 #define IDE_NATIVE_MODE 1
114 * @breif INCHIP Sata IDE Controller Mode
115 * NOTE: DO NOT ALLOW SATA & IDE use same mode
117 #define SATA_IDE_MODE IDE_LEGACY_MODE
120 * @def EXTERNAL_CLOCK
121 * @brief 00/10: Reference clock from crystal oscillator via
122 * PAD_XTALI and PAD_XTALO
124 * @def INTERNAL_CLOCK
125 * @brief 01/11: Reference clock from internal clock through
126 * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
128 #define EXTERNAL_CLOCK 0x00
129 #define INTERNAL_CLOCK 0x01
131 /* NOTE: inagua have to using internal clock,
132 * otherwise can not detect sata drive
134 #define SATA_CLOCK_SOURCE INTERNAL_CLOCK
137 * @def SATA_PORT_MULT_CAP_RESERVED
140 #define SATA_PORT_MULT_CAP_RESERVED 1
145 * @brief Detect Azalia controller automatically.
147 * @def AZALIA_DISABLE
148 * @brief Disable Azalia controller.
151 * @brief Enable Azalia controller.
153 #define AZALIA_AUTO 0
154 #define AZALIA_DISABLE 1
155 #define AZALIA_ENABLE 2
158 * @breif INCHIP HDA controller
160 #define AZALIA_CONTROLLER AZALIA_AUTO
163 * @def AZALIA_PIN_CONFIG
168 #define AZALIA_PIN_CONFIG 1
171 * @def AZALIA_SDIN_PIN
173 * SDIN0 is define at BIT0 & BIT1
176 * 10 - As a Azalia SDIN pin
177 * SDIN1 is define at BIT2 & BIT3
178 * SDIN2 is define at BIT4 & BIT5
179 * SDIN3 is define at BIT6 & BIT7
181 //#define AZALIA_SDIN_PIN 0xAA
182 #define AZALIA_SDIN_PIN 0x2A
185 * @def GPP_CONTROLLER
187 #define GPP_CONTROLLER CIMX_OPTION_ENABLED
191 * @brief GPP Link Configuration
192 * four possible configuration:
198 #define GPP_CFGMODE GPP_CFGMODE_X1111
205 #define NB_SB_GEN2 TRUE
212 #define SB_GPP_GEN2 TRUE
215 * @def SB_GPP_UNHIDE_PORTS
216 * TRUE - ports visable always, even port empty
217 * FALSE - ports invisable if port empty
219 #define SB_GPP_UNHIDE_PORTS FALSE
229 * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
231 #define SIO_HWM_BASE_ADDRESS 0x290