src/mainboard/asus/m5a99x-evo/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",           /* Output filename */
  23         "DSDT",                 /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "ASUS    ",               /* OEMID */
  26         "M5A99   ",          /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include "../../../arch/x86/acpi/debug.asl" */               /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, 0xE0000000)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* USB overcurrent mapping pins.   */
  45         Name(UOM0, 0)
  46         Name(UOM1, 2)
  47         Name(UOM2, 0)
  48         Name(UOM3, 7)
  49         Name(UOM4, 2)
  50         Name(UOM5, 2)
  51         Name(UOM6, 6)
  52         Name(UOM7, 2)
  53         Name(UOM8, 6)
  54         Name(UOM9, 6)
  55
  56         /* Some global data */
  57         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
  58         Name(OSV, Ones) /* Assume nothing */
  59         Name(PMOD, One) /* Assume APIC */
  60
  61         /*
  62          * Processor Object
  63          *
  64          */
  65         Scope (\_PR) {          /* define processor scope */
  66                 Processor(
  67                         CPU0,           /* name space name */
  68                         0,              /* Unique number for this processor */
  69                         0x808,          /* PBLK system I/O address !hardcoded! */
  70                         0x06            /* PBLKLEN for boot processor */
  71                         ) {
  72                         #include "acpi/cpstate.asl"
  73                 }
  74
  75                 Processor(
  76                         CPU1,           /* name space name */
  77                         1,              /* Unique number for this processor */
  78                         0x0000,         /* PBLK system I/O address !hardcoded! */
  79                         0x00            /* PBLKLEN for boot processor */
  80                         ) {
  81                         #include "acpi/cpstate.asl"
  82                 }
  83
  84                 Processor(
  85                         CPU2,           /* name space name */
  86                         2,              /* Unique number for this processor */
  87                         0x0000,         /* PBLK system I/O address !hardcoded! */
  88                         0x00            /* PBLKLEN for boot processor */
  89                         ) {
  90                         #include "acpi/cpstate.asl"
  91                 }
  92
  93                 Processor(
  94                         CPU3,           /* name space name */
  95                         3,              /* Unique number for this processor */
  96                         0x0000,         /* PBLK system I/O address !hardcoded! */
  97                         0x00            /* PBLKLEN for boot processor */
  98                         ) {
  99                         #include "acpi/cpstate.asl"
 100                 }
 101         } /* End _PR scope */
 102
 103         /* PIC IRQ mapping registers, C00h-C01h. */
 104         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 105                 Field(PRQM, ByteAcc, NoLock, Preserve) {
 106                 PRQI, 0x00000008,
 107                 PRQD, 0x00000008,  /* Offset: 1h */
 108         }
 109         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 110                 PIRA, 0x00000008,       /* Index 0 */
 111                 PIRB, 0x00000008,       /* Index 1 */
 112                 PIRC, 0x00000008,       /* Index 2 */
 113                 PIRD, 0x00000008,       /* Index 3 */
 114                 PIRE, 0x00000008,       /* Index 4 */
 115                 PIRF, 0x00000008,       /* Index 5 */
 116                 PIRG, 0x00000008,       /* Index 6 */
 117                 PIRH, 0x00000008,       /* Index 7 */
 118         }
 119
 120         /* PCI Error control register */
 121         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 122                 Field(PERC, ByteAcc, NoLock, Preserve) {
 123                 SENS, 0x00000001,
 124                 PENS, 0x00000001,
 125                 SENE, 0x00000001,
 126                 PENE, 0x00000001,
 127         }
 128
 129         /* Client Management index/data registers */
 130         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 131                 Field(CMT, ByteAcc, NoLock, Preserve) {
 132                 CMTI,      8,
 133                 /* Client Management Data register */
 134                 G64E,   1,
 135                 G64O,      1,
 136                 G32O,      2,
 137                 ,       2,
 138                 GPSL,     2,
 139         }
 140
 141         /* GPM Port register */
 142         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 143                 Field(GPT, ByteAcc, NoLock, Preserve) {
 144                 GPB0,1,
 145                 GPB1,1,
 146                 GPB2,1,
 147                 GPB3,1,
 148                 GPB4,1,
 149                 GPB5,1,
 150                 GPB6,1,
 151                 GPB7,1,
 152         }
 153
 154         /* Flash ROM program enable register */
 155         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 156                 Field(FRE, ByteAcc, NoLock, Preserve) {
 157                 ,     0x00000006,
 158                 FLRE, 0x00000001,
 159         }
 160
 161         /* PM2 index/data registers */
 162         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 163                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 164                 PM2I, 0x00000008,
 165                 PM2D, 0x00000008,
 166         }
 167
 168         /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
 169         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 170                 Field(PIOR, ByteAcc, NoLock, Preserve) {
 171                 PIOI, 0x00000008,
 172                 PIOD, 0x00000008,
 173         }
 174         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 175                 Offset(0x00),   /* MiscControl */
 176                 , 1,
 177                 T1EE, 1,
 178                 T2EE, 1,
 179                 Offset(0x01),   /* MiscStatus */
 180                 , 1,
 181                 T1E, 1,
 182                 T2E, 1,
 183                 Offset(0x04),   /* SmiWakeUpEventEnable3 */
 184                 , 7,
 185                 SSEN, 1,
 186                 Offset(0x07),   /* SmiWakeUpEventStatus3 */
 187                 , 7,
 188                 CSSM, 1,
 189                 Offset(0x10),   /* AcpiEnable */
 190                 , 6,
 191                 PWDE, 1,
 192                 Offset(0x1C),   /* ProgramIoEnable */
 193                 , 3,
 194                 MKME, 1,
 195                 IO3E, 1,
 196                 IO2E, 1,
 197                 IO1E, 1,
 198                 IO0E, 1,
 199                 Offset(0x1D),   /* IOMonitorStatus */
 200                 , 3,
 201                 MKMS, 1,
 202                 IO3S, 1,
 203                 IO2S, 1,
 204                 IO1S, 1,
 205                 IO0S,1,
 206                 Offset(0x20),   /* AcpiPmEvtBlk. TODO: should be 0x60 */
 207                 APEB, 16,
 208                 Offset(0x36),   /* GEvtLevelConfig */
 209                 , 6,
 210                 ELC6, 1,
 211                 ELC7, 1,
 212                 Offset(0x37),   /* GPMLevelConfig0 */
 213                 , 3,
 214                 PLC0, 1,
 215                 PLC1, 1,
 216                 PLC2, 1,
 217                 PLC3, 1,
 218                 PLC8, 1,
 219                 Offset(0x38),   /* GPMLevelConfig1 */
 220                 , 1,
 221                  PLC4, 1,
 222                  PLC5, 1,
 223                 , 1,
 224                  PLC6, 1,
 225                  PLC7, 1,
 226                 Offset(0x3B),   /* PMEStatus1 */
 227                 GP0S, 1,
 228                 GM4S, 1,
 229                 GM5S, 1,
 230                 APS, 1,
 231                 GM6S, 1,
 232                 GM7S, 1,
 233                 GP2S, 1,
 234                 STSS, 1,
 235                 Offset(0x55),   /* SoftPciRst */
 236                 SPRE, 1,
 237                 , 1,
 238                 , 1,
 239                 PNAT, 1,
 240                 PWMK, 1,
 241                 PWNS, 1,
 242
 243                 /*      Offset(0x61), */        /*  Options_1 */
 244                 /*              ,7,  */
 245                 /*              R617,1, */
 246
 247                 Offset(0x65),   /* UsbPMControl */
 248                 , 4,
 249                 URRE, 1,
 250                 Offset(0x68),   /* MiscEnable68 */
 251                 , 3,
 252                 TMTE, 1,
 253                 , 1,
 254                 Offset(0x92),   /* GEVENTIN */
 255                 , 7,
 256                 E7IS, 1,
 257                 Offset(0x96),   /* GPM98IN */
 258                 G8IS, 1,
 259                 G9IS, 1,
 260                 Offset(0x9A),   /* EnhanceControl */
 261                 ,7,
 262                 HPDE, 1,
 263                 Offset(0xA8),   /* PIO7654Enable */
 264                 IO4E, 1,
 265                 IO5E, 1,
 266                 IO6E, 1,
 267                 IO7E, 1,
 268                 Offset(0xA9),   /* PIO7654Status */
 269                 IO4S, 1,
 270                 IO5S, 1,
 271                 IO6S, 1,
 272                 IO7S, 1,
 273         }
 274
 275         /* PM1 Event Block
 276         * First word is PM1_Status, Second word is PM1_Enable
 277         */
 278         OperationRegion(P1EB, SystemIO, APEB, 0x04)
 279                 Field(P1EB, ByteAcc, NoLock, Preserve) {
 280                 TMST, 1,
 281                 ,    3,
 282                 BMST,    1,
 283                 GBST,   1,
 284                 Offset(0x01),
 285                 PBST, 1,
 286                 , 1,
 287                 RTST, 1,
 288                 , 3,
 289                 PWST, 1,
 290                 SPWS, 1,
 291                 Offset(0x02),
 292                 TMEN, 1,
 293                 , 4,
 294                 GBEN, 1,
 295                 Offset(0x03),
 296                 PBEN, 1,
 297                 , 1,
 298                 RTEN, 1,
 299                 , 3,
 300                 PWDA, 1,
 301         }
 302
 303         Scope(\_SB) {
 304                 /* PCIe Configuration Space for 16 busses */
 305                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 306                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 307                         /* Byte offsets are computed using the following technique:
 308                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 309                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 310                         */
 311                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 312                         STB5, 32,
 313                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 314                         PT0D, 1,
 315                         PT1D, 1,
 316                         PT2D, 1,
 317                         PT3D, 1,
 318                         PT4D, 1,
 319                         PT5D, 1,
 320                         PT6D, 1,
 321                         PT7D, 1,
 322                         PT8D, 1,
 323                         PT9D, 1,
 324                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 325                         SBIE, 1,
 326                         SBME, 1,
 327                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 328                         SBRI, 8,
 329                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 330                         SBB1, 32,
 331                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 332                         ,14,
 333                         P92E, 1,                /* Port92 decode enable */
 334                 }
 335
 336                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 337                         Field(SB5, AnyAcc, NoLock, Preserve){
 338                         /* Port 0 */
 339                         Offset(0x120),          /* Port 0 Task file status */
 340                         P0ER, 1,
 341                         , 2,
 342                         P0DQ, 1,
 343                         , 3,
 344                         P0BY, 1,
 345                         Offset(0x128),          /* Port 0 Serial ATA status */
 346                         P0DD, 4,
 347                         , 4,
 348                         P0IS, 4,
 349                         Offset(0x12C),          /* Port 0 Serial ATA control */
 350                         P0DI, 4,
 351                         Offset(0x130),          /* Port 0 Serial ATA error */
 352                         , 16,
 353                         P0PR, 1,
 354
 355                         /* Port 1 */
 356                         offset(0x1A0),          /* Port 1 Task file status */
 357                         P1ER, 1,
 358                         , 2,
 359                         P1DQ, 1,
 360                         , 3,
 361                         P1BY, 1,
 362                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 363                         P1DD, 4,
 364                         , 4,
 365                         P1IS, 4,
 366                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 367                         P1DI, 4,
 368                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 369                         , 16,
 370                         P1PR, 1,
 371
 372                         /* Port 2 */
 373                         Offset(0x220),          /* Port 2 Task file status */
 374                         P2ER, 1,
 375                         , 2,
 376                         P2DQ, 1,
 377                         , 3,
 378                         P2BY, 1,
 379                         Offset(0x228),          /* Port 2 Serial ATA status */
 380                         P2DD, 4,
 381                         , 4,
 382                         P2IS, 4,
 383                         Offset(0x22C),          /* Port 2 Serial ATA control */
 384                         P2DI, 4,
 385                         Offset(0x230),          /* Port 2 Serial ATA error */
 386                         , 16,
 387                         P2PR, 1,
 388
 389                         /* Port 3 */
 390                         Offset(0x2A0),          /* Port 3 Task file status */
 391                         P3ER, 1,
 392                         , 2,
 393                         P3DQ, 1,
 394                         , 3,
 395                         P3BY, 1,
 396                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 397                         P3DD, 4,
 398                         , 4,
 399                         P3IS, 4,
 400                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 401                         P3DI, 4,
 402                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 403                         , 16,
 404                         P3PR, 1,
 405                 }
 406         }
 407
 408
 409         #include "acpi/routing.asl"
 410
 411         Scope(\_SB) {
 412
 413                 Method(CkOT, 0){
 414
 415                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
 416
 417                         if(CondRefOf(\_OSI,Local1))
 418                         {
 419                                 Store(1, OSTP)                /* Assume some form of XP */
 420                                 if (\_OSI("Windows 2006"))      /* Vista */
 421                                 {
 422                                         Store(2, OSTP)
 423                                 }
 424                         } else {
 425                                 If(WCMP(\_OS,"Linux")) {
 426                                         Store(3, OSTP)            /* Linux */
 427                                 } Else {
 428                                         Store(4, OSTP)            /* Gotta be WinCE */
 429                                 }
 430                         }
 431                         Return(OSTP)
 432                 }
 433
 434                 Method(_PIC, 0x01, NotSerialized)
 435                 {
 436                         If (Arg0)
 437                         {
 438                                 \_SB.CIRQ()
 439                         }
 440                         Store(Arg0, PMOD)
 441                 }
 442                 Method(CIRQ, 0x00, NotSerialized){
 443                         Store(0, PIRA)
 444                         Store(0, PIRB)
 445                         Store(0, PIRC)
 446                         Store(0, PIRD)
 447                         Store(0, PIRE)
 448                         Store(0, PIRF)
 449                         Store(0, PIRG)
 450                         Store(0, PIRH)
 451                 }
 452
 453                 Name(IRQB, ResourceTemplate(){
 454                         IRQ(Level,ActiveLow,Shared){15}
 455                 })
 456
 457                 Name(IRQP, ResourceTemplate(){
 458                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
 459                 })
 460
 461                 Name(PITF, ResourceTemplate(){
 462                         IRQ(Level,ActiveLow,Exclusive){9}
 463                 })
 464
 465                 Device(INTA) {
 466                         Name(_HID, EISAID("PNP0C0F"))
 467                         Name(_UID, 1)
 468
 469                         Method(_STA, 0) {
 470                                 if (PIRA) {
 471                                         Return(0x0B) /* sata is invisible */
 472                                 } else {
 473                                         Return(0x09) /* sata is disabled */
 474                                 }
 475                         } /* End Method(_SB.INTA._STA) */
 476
 477                         Method(_DIS ,0) {
 478                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
 479                                 Store(0, PIRA)
 480                         } /* End Method(_SB.INTA._DIS) */
 481
 482                         Method(_PRS ,0) {
 483                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
 484                                 Return(IRQP)
 485                         } /* Method(_SB.INTA._PRS) */
 486
 487                         Method(_CRS ,0) {
 488                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 489                                 CreateWordField(IRQB, 0x1, IRQN)
 490                                 ShiftLeft(1, PIRA, IRQN)
 491                                 Return(IRQB)
 492                         } /* Method(_SB.INTA._CRS) */
 493
 494                         Method(_SRS, 1) {
 495                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 496                                 CreateWordField(ARG0, 1, IRQM)
 497
 498                                 /* Use lowest available IRQ */
 499                                 FindSetRightBit(IRQM, Local0)
 500                                 if (Local0) {
 501                                         Decrement(Local0)
 502                                 }
 503                                 Store(Local0, PIRA)
 504                         } /* End Method(_SB.INTA._SRS) */
 505                 } /* End Device(INTA) */
 506
 507                 Device(INTB) {
 508                         Name(_HID, EISAID("PNP0C0F"))
 509                         Name(_UID, 2)
 510
 511                         Method(_STA, 0) {
 512                                 if (PIRB) {
 513                                         Return(0x0B) /* sata is invisible */
 514                                 } else {
 515                                         Return(0x09) /* sata is disabled */
 516                                 }
 517                         } /* End Method(_SB.INTB._STA) */
 518
 519                         Method(_DIS ,0) {
 520                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
 521                                 Store(0, PIRB)
 522                         } /* End Method(_SB.INTB._DIS) */
 523
 524                         Method(_PRS ,0) {
 525                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
 526                                 Return(IRQP)
 527                         } /* Method(_SB.INTB._PRS) */
 528
 529                         Method(_CRS ,0) {
 530                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 531                                 CreateWordField(IRQB, 0x1, IRQN)
 532                                 ShiftLeft(1, PIRB, IRQN)
 533                                 Return(IRQB)
 534                         } /* Method(_SB.INTB._CRS) */
 535
 536                         Method(_SRS, 1) {
 537                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 538                                 CreateWordField(ARG0, 1, IRQM)
 539
 540                                 /* Use lowest available IRQ */
 541                                 FindSetRightBit(IRQM, Local0)
 542                                 if (Local0) {
 543                                         Decrement(Local0)
 544                                 }
 545                                 Store(Local0, PIRB)
 546                         } /* End Method(_SB.INTB._SRS) */
 547                 } /* End Device(INTB)  */
 548
 549                 Device(INTC) {
 550                         Name(_HID, EISAID("PNP0C0F"))
 551                         Name(_UID, 3)
 552
 553                         Method(_STA, 0) {
 554                                 if (PIRC) {
 555                                         Return(0x0B) /* sata is invisible */
 556                                 } else {
 557                                         Return(0x09) /* sata is disabled */
 558                                 }
 559                         } /* End Method(_SB.INTC._STA) */
 560
 561                         Method(_DIS ,0) {
 562                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
 563                                 Store(0, PIRC)
 564                         } /* End Method(_SB.INTC._DIS) */
 565
 566                         Method(_PRS ,0) {
 567                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
 568                                 Return(IRQP)
 569                         } /* Method(_SB.INTC._PRS) */
 570
 571                         Method(_CRS ,0) {
 572                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 573                                 CreateWordField(IRQB, 0x1, IRQN)
 574                                 ShiftLeft(1, PIRC, IRQN)
 575                                 Return(IRQB)
 576                         } /* Method(_SB.INTC._CRS) */
 577
 578                         Method(_SRS, 1) {
 579                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 580                                 CreateWordField(ARG0, 1, IRQM)
 581
 582                                 /* Use lowest available IRQ */
 583                                 FindSetRightBit(IRQM, Local0)
 584                                 if (Local0) {
 585                                         Decrement(Local0)
 586                                 }
 587                                 Store(Local0, PIRC)
 588                         } /* End Method(_SB.INTC._SRS) */
 589                 } /* End Device(INTC)  */
 590
 591                 Device(INTD) {
 592                         Name(_HID, EISAID("PNP0C0F"))
 593                         Name(_UID, 4)
 594
 595                         Method(_STA, 0) {
 596                                 if (PIRD) {
 597                                         Return(0x0B) /* sata is invisible */
 598                                 } else {
 599                                         Return(0x09) /* sata is disabled */
 600                                 }
 601                         } /* End Method(_SB.INTD._STA) */
 602
 603                         Method(_DIS ,0) {
 604                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
 605                                 Store(0, PIRD)
 606                         } /* End Method(_SB.INTD._DIS) */
 607
 608                         Method(_PRS ,0) {
 609                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
 610                                 Return(IRQP)
 611                         } /* Method(_SB.INTD._PRS) */
 612
 613                         Method(_CRS ,0) {
 614                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 615                                 CreateWordField(IRQB, 0x1, IRQN)
 616                                 ShiftLeft(1, PIRD, IRQN)
 617                                 Return(IRQB)
 618                         } /* Method(_SB.INTD._CRS) */
 619
 620                         Method(_SRS, 1) {
 621                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 622                                 CreateWordField(ARG0, 1, IRQM)
 623
 624                                 /* Use lowest available IRQ */
 625                                 FindSetRightBit(IRQM, Local0)
 626                                 if (Local0) {
 627                                         Decrement(Local0)
 628                                 }
 629                                 Store(Local0, PIRD)
 630                         } /* End Method(_SB.INTD._SRS) */
 631                 } /* End Device(INTD)  */
 632
 633                 Device(INTE) {
 634                         Name(_HID, EISAID("PNP0C0F"))
 635                         Name(_UID, 5)
 636
 637                         Method(_STA, 0) {
 638                                 if (PIRE) {
 639                                         Return(0x0B) /* sata is invisible */
 640                                 } else {
 641                                         Return(0x09) /* sata is disabled */
 642                                 }
 643                         } /* End Method(_SB.INTE._STA) */
 644
 645                         Method(_DIS ,0) {
 646                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
 647                                 Store(0, PIRE)
 648                         } /* End Method(_SB.INTE._DIS) */
 649
 650                         Method(_PRS ,0) {
 651                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
 652                                 Return(IRQP)
 653                         } /* Method(_SB.INTE._PRS) */
 654
 655                         Method(_CRS ,0) {
 656                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 657                                 CreateWordField(IRQB, 0x1, IRQN)
 658                                 ShiftLeft(1, PIRE, IRQN)
 659                                 Return(IRQB)
 660                         } /* Method(_SB.INTE._CRS) */
 661
 662                         Method(_SRS, 1) {
 663                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 664                                 CreateWordField(ARG0, 1, IRQM)
 665
 666                                 /* Use lowest available IRQ */
 667                                 FindSetRightBit(IRQM, Local0)
 668                                 if (Local0) {
 669                                         Decrement(Local0)
 670                                 }
 671                                 Store(Local0, PIRE)
 672                         } /* End Method(_SB.INTE._SRS) */
 673                 } /* End Device(INTE)  */
 674
 675                 Device(INTF) {
 676                         Name(_HID, EISAID("PNP0C0F"))
 677                         Name(_UID, 6)
 678
 679                         Method(_STA, 0) {
 680                                 if (PIRF) {
 681                                         Return(0x0B) /* sata is invisible */
 682                                 } else {
 683                                         Return(0x09) /* sata is disabled */
 684                                 }
 685                         } /* End Method(_SB.INTF._STA) */
 686
 687                         Method(_DIS ,0) {
 688                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
 689                                 Store(0, PIRF)
 690                         } /* End Method(_SB.INTF._DIS) */
 691
 692                         Method(_PRS ,0) {
 693                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
 694                                 Return(PITF)
 695                         } /* Method(_SB.INTF._PRS) */
 696
 697                         Method(_CRS ,0) {
 698                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 699                                 CreateWordField(IRQB, 0x1, IRQN)
 700                                 ShiftLeft(1, PIRF, IRQN)
 701                                 Return(IRQB)
 702                         } /* Method(_SB.INTF._CRS) */
 703
 704                         Method(_SRS, 1) {
 705                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 706                                 CreateWordField(ARG0, 1, IRQM)
 707
 708                                 /* Use lowest available IRQ */
 709                                 FindSetRightBit(IRQM, Local0)
 710                                 if (Local0) {
 711                                         Decrement(Local0)
 712                                 }
 713                                 Store(Local0, PIRF)
 714                         } /*  End Method(_SB.INTF._SRS) */
 715                 } /* End Device(INTF)  */
 716
 717                 Device(INTG) {
 718                         Name(_HID, EISAID("PNP0C0F"))
 719                         Name(_UID, 7)
 720
 721                         Method(_STA, 0) {
 722                                 if (PIRG) {
 723                                         Return(0x0B) /* sata is invisible */
 724                                 } else {
 725                                         Return(0x09) /* sata is disabled */
 726                                 }
 727                         } /* End Method(_SB.INTG._STA)  */
 728
 729                         Method(_DIS ,0) {
 730                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
 731                                 Store(0, PIRG)
 732                         } /* End Method(_SB.INTG._DIS)  */
 733
 734                         Method(_PRS ,0) {
 735                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
 736                                 Return(IRQP)
 737                         } /* Method(_SB.INTG._CRS)  */
 738
 739                         Method(_CRS ,0) {
 740                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 741                                 CreateWordField(IRQB, 0x1, IRQN)
 742                                 ShiftLeft(1, PIRG, IRQN)
 743                                 Return(IRQB)
 744                         } /* Method(_SB.INTG._CRS)  */
 745
 746                         Method(_SRS, 1) {
 747                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 748                                 CreateWordField(ARG0, 1, IRQM)
 749
 750                                 /* Use lowest available IRQ */
 751                                 FindSetRightBit(IRQM, Local0)
 752                                 if (Local0) {
 753                                         Decrement(Local0)
 754                                 }
 755                                 Store(Local0, PIRG)
 756                         } /* End Method(_SB.INTG._SRS)  */
 757                 } /* End Device(INTG)  */
 758
 759                 Device(INTH) {
 760                         Name(_HID, EISAID("PNP0C0F"))
 761                         Name(_UID, 8)
 762
 763                         Method(_STA, 0) {
 764                                 if (PIRH) {
 765                                         Return(0x0B) /* sata is invisible */
 766                                 } else {
 767                                         Return(0x09) /* sata is disabled */
 768                                 }
 769                         } /* End Method(_SB.INTH._STA)  */
 770
 771                         Method(_DIS ,0) {
 772                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
 773                                 Store(0, PIRH)
 774                         } /* End Method(_SB.INTH._DIS)  */
 775
 776                         Method(_PRS ,0) {
 777                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
 778                                 Return(IRQP)
 779                         } /* Method(_SB.INTH._CRS)  */
 780
 781                         Method(_CRS ,0) {
 782                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 783                                 CreateWordField(IRQB, 0x1, IRQN)
 784                                 ShiftLeft(1, PIRH, IRQN)
 785                                 Return(IRQB)
 786                         } /* Method(_SB.INTH._CRS)  */
 787
 788                         Method(_SRS, 1) {
 789                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 790                                 CreateWordField(ARG0, 1, IRQM)
 791
 792                                 /* Use lowest available IRQ */
 793                                 FindSetRightBit(IRQM, Local0)
 794                                 if (Local0) {
 795                                         Decrement(Local0)
 796                                 }
 797                                 Store(Local0, PIRH)
 798                         } /* End Method(_SB.INTH._SRS)  */
 799                 } /* End Device(INTH)   */
 800
 801         }   /* End Scope(_SB)  */
 802
 803
 804         /* Supported sleep states: */
 805         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 806
 807         If (LAnd(SSFG, 0x01)) {
 808                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 809         }
 810         If (LAnd(SSFG, 0x02)) {
 811                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 812         }
 813         If (LAnd(SSFG, 0x04)) {
 814                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 815         }
 816         If (LAnd(SSFG, 0x08)) {
 817                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 818         }
 819
 820         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 821
 822         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 823         Name(CSMS, 0)                   /* Current System State */
 824
 825         /* Wake status package */
 826         Name(WKST,Package(){Zero, Zero})
 827
 828         /*
 829         * \_PTS - Prepare to Sleep method
 830         *
 831         *       Entry:
 832         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 833         *
 834         * Exit:
 835         *               -none-
 836         *
 837         * The _PTS control method is executed at the beginning of the sleep process
 838         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 839         * control method may be executed a relatively long time before entering the
 840         * sleep state and the OS may abort      the operation without notification to
 841         * the ACPI driver.  This method cannot modify the configuration or power
 842         * state of any device in the system.
 843         */
 844         Method(\_PTS, 1) {
 845                 /* DBGO("\\_PTS\n") */
 846                 /* DBGO("From S0 to S") */
 847                 /* DBGO(Arg0) */
 848                 /* DBGO("\n") */
 849
 850                 /* Don't allow PCIRST# to reset USB */
 851                 if (LEqual(Arg0,3)){
 852                         Store(0,URRE)
 853                 }
 854
 855                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 856                 /*Store(One, CSSM)
 857                 Store(One, SSEN)*/
 858
 859                 /* On older chips, clear PciExpWakeDisEn */
 860                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 861                 *       Store(0,\_SB.PWDE)
 862                 *}
 863                 */
 864
 865                 /* Clear wake status structure. */
 866                 Store(0, Index(WKST,0))
 867                 Store(0, Index(WKST,1))
 868         } /* End Method(\_PTS) */
 869
 870         /*
 871         *  The following method results in a "not a valid reserved NameSeg"
 872         *  warning so I have commented it out for the duration.  It isn't
 873         *  used, so it could be removed.
 874         *
 875         *
 876         *       \_GTS OEM Going To Sleep method
 877         *
 878         *       Entry:
 879         *               Arg0=The value of the sleeping state S1=1, S2=2
 880         *
 881         *       Exit:
 882         *               -none-
 883         *
 884         *  Method(\_GTS, 1) {
 885         *  DBGO("\\_GTS\n")
 886         *  DBGO("From S0 to S")
 887         *  DBGO(Arg0)
 888         *  DBGO("\n")
 889         *  }
 890         */
 891
 892         /*
 893         *       \_BFS OEM Back From Sleep method
 894         *
 895         *       Entry:
 896         *               Arg0=The value of the sleeping state S1=1, S2=2
 897         *
 898         *       Exit:
 899         *               -none-
 900         */
 901         Method(\_BFS, 1) {
 902                 /* DBGO("\\_BFS\n") */
 903                 /* DBGO("From S") */
 904                 /* DBGO(Arg0) */
 905                 /* DBGO(" to S0\n") */
 906         }
 907
 908         /*
 909         *  \_WAK System Wake method
 910         *
 911         *       Entry:
 912         *               Arg0=The value of the sleeping state S1=1, S2=2
 913         *
 914         *       Exit:
 915         *               Return package of 2 DWords
 916         *               Dword 1 - Status
 917         *                       0x00000000      wake succeeded
 918         *                       0x00000001      Wake was signaled but failed due to lack of power
 919         *                       0x00000002      Wake was signaled but failed due to thermal condition
 920         *               Dword 2 - Power Supply state
 921         *                       if non-zero the effective S-state the power supply entered
 922         */
 923         Method(\_WAK, 1) {
 924                 /* DBGO("\\_WAK\n") */
 925                 /* DBGO("From S") */
 926                 /* DBGO(Arg0) */
 927                 /* DBGO(" to S0\n") */
 928
 929                 /* Re-enable HPET */
 930                 Store(1,HPDE)
 931
 932                 /* Restore PCIRST# so it resets USB */
 933                 if (LEqual(Arg0,3)){
 934                         Store(1,URRE)
 935                 }
 936
 937                 /* Arbitrarily clear PciExpWakeStatus */
 938                 Store(PWST, PWST)
 939
 940                 /* if(DeRefOf(Index(WKST,0))) {
 941                 *       Store(0, Index(WKST,1))
 942                 * } else {
 943                 *       Store(Arg0, Index(WKST,1))
 944                 * }
 945                 */
 946                 Return(WKST)
 947         } /* End Method(\_WAK) */
 948
 949         Scope(\_GPE) {  /* Start Scope GPE */
 950                 /*  General event 0  */
 951                 /* Method(_L00) {
 952                 *       DBGO("\\_GPE\\_L00\n")
 953                 * }
 954                 */
 955
 956                 /*  General event 1  */
 957                 /* Method(_L01) {
 958                 *       DBGO("\\_GPE\\_L00\n")
 959                 * }
 960                 */
 961
 962                 /*  General event 2  */
 963                 /* Method(_L02) {
 964                 *       DBGO("\\_GPE\\_L00\n")
 965                 * }
 966                 */
 967
 968                 /*  General event 3  */
 969                 Method(_L03) {
 970                         /* DBGO("\\_GPE\\_L00\n") */
 971                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 972                 }
 973
 974                 /*  General event 4  */
 975                 /* Method(_L04) {
 976                 *       DBGO("\\_GPE\\_L00\n")
 977                 * }
 978                 */
 979
 980                 /*  General event 5  */
 981                 /* Method(_L05) {
 982                 *       DBGO("\\_GPE\\_L00\n")
 983                 * }
 984                 */
 985
 986                 /*  General event 6 - Used for GPM6, moved to USB.asl */
 987                 /* Method(_L06) {
 988                 *       DBGO("\\_GPE\\_L00\n")
 989                 * }
 990                 */
 991
 992                 /*  General event 7 - Used for GPM7, moved to USB.asl */
 993                 /* Method(_L07) {
 994                 *       DBGO("\\_GPE\\_L07\n")
 995                 * }
 996                 */
 997
 998                 /*  Legacy PM event  */
 999                 Method(_L08) {
1000                         /* DBGO("\\_GPE\\_L08\n") */
1001                 }
1002
1003                 /*  Temp warning (TWarn) event  */
1004                 Method(_L09) {
1005                         /* DBGO("\\_GPE\\_L09\n") */
1006                         /* Notify (\_TZ.TZ00, 0x80) */
1007                 }
1008
1009                 /*  Reserved  */
1010                 /* Method(_L0A) {
1011                 *       DBGO("\\_GPE\\_L0A\n")
1012                 * }
1013                 */
1014
1015                 /*  USB controller PME#  */
1016                 Method(_L0B) {
1017                         /* DBGO("\\_GPE\\_L0B\n") */
1018                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1019                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1020                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1021                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1022                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1023                         Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1024                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1025                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1026                 }
1027
1028                 /*  AC97 controller PME#  */
1029                 /* Method(_L0C) {
1030                 *       DBGO("\\_GPE\\_L0C\n")
1031                 * }
1032                 */
1033
1034                 /*  OtherTherm PME#  */
1035                 /* Method(_L0D) {
1036                 *       DBGO("\\_GPE\\_L0D\n")
1037                 * }
1038                 */
1039
1040                 /*  GPM9 SCI event - Moved to USB.asl */
1041                 /* Method(_L0E) {
1042                 *       DBGO("\\_GPE\\_L0E\n")
1043                 * }
1044                 */
1045
1046                 /*  PCIe HotPlug event  */
1047                 /* Method(_L0F) {
1048                 *       DBGO("\\_GPE\\_L0F\n")
1049                 * }
1050                 */
1051
1052                 /*  ExtEvent0 SCI event  */
1053                 Method(_L10) {
1054                         /* DBGO("\\_GPE\\_L10\n") */
1055                 }
1056
1057
1058                 /*  ExtEvent1 SCI event  */
1059                 Method(_L11) {
1060                         /* DBGO("\\_GPE\\_L11\n") */
1061                 }
1062
1063                 /*  PCIe PME# event  */
1064                 /* Method(_L12) {
1065                 *       DBGO("\\_GPE\\_L12\n")
1066                 * }
1067                 */
1068
1069                 /*  GPM0 SCI event - Moved to USB.asl */
1070                 /* Method(_L13) {
1071                 *       DBGO("\\_GPE\\_L13\n")
1072                 * }
1073                 */
1074
1075                 /*  GPM1 SCI event - Moved to USB.asl */
1076                 /* Method(_L14) {
1077                 *       DBGO("\\_GPE\\_L14\n")
1078                 * }
1079                 */
1080
1081                 /*  GPM2 SCI event - Moved to USB.asl */
1082                 /* Method(_L15) {
1083                 *       DBGO("\\_GPE\\_L15\n")
1084                 * }
1085                 */
1086
1087                 /*  GPM3 SCI event - Moved to USB.asl */
1088                 /* Method(_L16) {
1089                 *       DBGO("\\_GPE\\_L16\n")
1090                 * }
1091                 */
1092
1093                 /*  GPM8 SCI event - Moved to USB.asl */
1094                 /* Method(_L17) {
1095                 *       DBGO("\\_GPE\\_L17\n")
1096                 * }
1097                 */
1098
1099                 /*  GPIO0 or GEvent8 event  */
1100                 Method(_L18) {
1101                         /* DBGO("\\_GPE\\_L18\n") */
1102                         Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1103                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1104                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1105                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1106                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1107                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1108                 }
1109
1110                 /*  GPM4 SCI event - Moved to USB.asl */
1111                 /* Method(_L19) {
1112                 *       DBGO("\\_GPE\\_L19\n")
1113                 * }
1114                 */
1115
1116                 /*  GPM5 SCI event - Moved to USB.asl */
1117                 /* Method(_L1A) {
1118                 *       DBGO("\\_GPE\\_L1A\n")
1119                 * }
1120                 */
1121
1122                 /*  Azalia SCI event  */
1123                 Method(_L1B) {
1124                         /* DBGO("\\_GPE\\_L1B\n") */
1125                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1126                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1127                 }
1128
1129                 /*  GPM6 SCI event - Reassigned to _L06 */
1130                 /* Method(_L1C) {
1131                 *       DBGO("\\_GPE\\_L1C\n")
1132                 * }
1133                 */
1134
1135                 /*  GPM7 SCI event - Reassigned to _L07 */
1136                 /* Method(_L1D) {
1137                 *       DBGO("\\_GPE\\_L1D\n")
1138                 * }
1139                 */
1140
1141                 /*  GPIO2 or GPIO66 SCI event  */
1142                 /* Method(_L1E) {
1143                 *       DBGO("\\_GPE\\_L1E\n")
1144                 * }
1145                 */
1146
1147                 /*  SATA SCI event - Moved to sata.asl */
1148                 /* Method(_L1F) {
1149                 *        DBGO("\\_GPE\\_L1F\n")
1150                 * }
1151                 */
1152
1153         }       /* End Scope GPE */
1154
1155         #include "acpi/usb.asl"
1156
1157         /* South Bridge */
1158         Scope(\_SB) { /* Start \_SB scope */
1159                 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1160
1161                 /*  _SB.PCI0 */
1162                 /* Note: Only need HID on Primary Bus */
1163                 Device(PCI0) {
1164                         External (TOM1)
1165                         External (TOM2)
1166                         Name(_HID, EISAID("PNP0A03"))
1167                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1168                         Method(_BBN, 0) { /* Bus number = 0 */
1169                                 Return(0)
1170                         }
1171                         Method(_STA, 0) {
1172                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1173                                 Return(0x0B)     /* Status is visible */
1174                         }
1175
1176                         Method(_PRT,0) {
1177                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1178                                 Return (PR0)                  /* PIC Mode */
1179                         } /* end _PRT */
1180
1181                         /* Describe the Northbridge devices */
1182                         Device(AMRT) {
1183                                 Name(_ADR, 0x00000000)
1184                         } /* end AMRT */
1185
1186                         /* The internal GFX bridge */
1187                         Device(AGPB) {
1188                                 Name(_ADR, 0x00010000)
1189                                 Name(_PRW, Package() {0x18, 4})
1190                                 Method(_PRT,0) {
1191                                         Return (APR1)
1192                                 }
1193                         }  /* end AGPB */
1194
1195                         /* The external GFX bridge */
1196                         Device(PBR2) {
1197                                 Name(_ADR, 0x00020000)
1198                                 Name(_PRW, Package() {0x18, 4})
1199                                 Method(_PRT,0) {
1200                                         If(PMOD){ Return(APS2) }   /* APIC mode */
1201                                         Return (PS2)                  /* PIC Mode */
1202                                 } /* end _PRT */
1203                         } /* end PBR2 */
1204
1205                         /* Dev3 is also an external GFX bridge, not used in Herring */
1206
1207                         Device(PBR4) {
1208                                 Name(_ADR, 0x00040000)
1209                                 Name(_PRW, Package() {0x18, 4})
1210                                 Method(_PRT,0) {
1211                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1212                                         Return (PS4)                  /* PIC Mode */
1213                                 } /* end _PRT */
1214                         } /* end PBR4 */
1215
1216                         Device(PBR5) {
1217                                 Name(_ADR, 0x00050000)
1218                                 Name(_PRW, Package() {0x18, 4})
1219                                 Method(_PRT,0) {
1220                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1221                                         Return (PS5)                  /* PIC Mode */
1222                                 } /* end _PRT */
1223                         } /* end PBR5 */
1224
1225                         Device(PBR6) {
1226                                 Name(_ADR, 0x00060000)
1227                                 Name(_PRW, Package() {0x18, 4})
1228                                 Method(_PRT,0) {
1229                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1230                                         Return (PS6)                  /* PIC Mode */
1231                                 } /* end _PRT */
1232                         } /* end PBR6 */
1233
1234                         /* The onboard EtherNet chip */
1235                         Device(PBR7) {
1236                                 Name(_ADR, 0x00070000)
1237                                 Name(_PRW, Package() {0x18, 4})
1238                                 Method(_PRT,0) {
1239                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1240                                         Return (PS7)                  /* PIC Mode */
1241                                 } /* end _PRT */
1242                         } /* end PBR7 */
1243
1244                         /* GPP */
1245                         Device(PBR9) {
1246                                 Name(_ADR, 0x00090000)
1247                                 Name(_PRW, Package() {0x18, 4})
1248                                 Method(_PRT,0) {
1249                                         If(PMOD){ Return(APS9) }   /* APIC mode */
1250                                         Return (PS9)                  /* PIC Mode */
1251                                 } /* end _PRT */
1252                         } /* end PBR9 */
1253
1254                         Device(PBRa) {
1255                                 Name(_ADR, 0x000A0000)
1256                                 Name(_PRW, Package() {0x18, 4})
1257                                 Method(_PRT,0) {
1258                                         If(PMOD){ Return(APSa) }   /* APIC mode */
1259                                         Return (PSa)                  /* PIC Mode */
1260                                 } /* end _PRT */
1261                         } /* end PBRa */
1262
1263                         Device(PE20) {
1264                                 Name(_ADR, 0x00150000)
1265                                 Name(_PRW, Package() {0x18, 4})
1266                                 Method(_PRT,0) {
1267                                         If(PMOD){ Return(APE0) }   /* APIC mode */
1268                                         Return (PE0)                  /* PIC Mode */
1269                                 } /* end _PRT */
1270                         } /* end PE20 */
1271                         Device(PE21) {
1272                                 Name(_ADR, 0x00150001)
1273                                 Name(_PRW, Package() {0x18, 4})
1274                                 Method(_PRT,0) {
1275                                         If(PMOD){ Return(APE1) }   /* APIC mode */
1276                                         Return (PE1)                  /* PIC Mode */
1277                                 } /* end _PRT */
1278                         } /* end PE21 */
1279                         Device(PE22) {
1280                                 Name(_ADR, 0x00150002)
1281                                 Name(_PRW, Package() {0x18, 4})
1282                                 Method(_PRT,0) {
1283                                         If(PMOD){ Return(APE2) }   /* APIC mode */
1284                                         Return (APE2)                  /* PIC Mode */
1285                                 } /* end _PRT */
1286                         } /* end PE22 */
1287                         Device(PE23) {
1288                                 Name(_ADR, 0x00150003)
1289                                 Name(_PRW, Package() {0x18, 4})
1290                                 Method(_PRT,0) {
1291                                         If(PMOD){ Return(APE3) }   /* APIC mode */
1292                                         Return (PE3)                  /* PIC Mode */
1293                                 } /* end _PRT */
1294                         } /* end PE23 */
1295
1296                         /* PCI slot 1, 2, 3 */
1297                         Device(PIBR) {
1298                                 Name(_ADR, 0x00140004)
1299                                 Name(_PRW, Package() {0x18, 4})
1300
1301                                 Method(_PRT, 0) {
1302                                         Return (PCIB)
1303                                 }
1304                         }
1305
1306                         /* Describe the Southbridge devices */
1307                         Device(STCR) {
1308                                 Name(_ADR, 0x00110000)
1309                                 #include "acpi/sata.asl"
1310                         } /* end STCR */
1311
1312                         Device(UOH1) {
1313                                 Name(_ADR, 0x00120000)
1314                                 Name(_PRW, Package() {0x0B, 3})
1315                         } /* end UOH1 */
1316
1317                         Device(UOH2) {
1318                                 Name(_ADR, 0x00120002)
1319                                 Name(_PRW, Package() {0x0B, 3})
1320                         } /* end UOH2 */
1321
1322                         Device(UOH3) {
1323                                 Name(_ADR, 0x00130000)
1324                                 Name(_PRW, Package() {0x0B, 3})
1325                         } /* end UOH3 */
1326
1327                         Device(UOH4) {
1328                                 Name(_ADR, 0x00130002)
1329                                 Name(_PRW, Package() {0x0B, 3})
1330                         } /* end UOH4 */
1331
1332                         Device(UOH5) {
1333                                 Name(_ADR, 0x00160000)
1334                                 Name(_PRW, Package() {0x0B, 3})
1335                         } /* end UOH5 */
1336
1337                         Device(UOH6) {
1338                                 Name(_ADR, 0x00160002)
1339                                 Name(_PRW, Package() {0x0B, 3})
1340                         } /* end UOH5 */
1341
1342                         Device(UEH1) {
1343                                 Name(_ADR, 0x00140005)
1344                                 Name(_PRW, Package() {0x0B, 3})
1345                         } /* end UEH1 */
1346
1347                         Device(SBUS) {
1348                                 Name(_ADR, 0x00140000)
1349                         } /* end SBUS */
1350
1351                         /* Primary (and only) IDE channel */
1352                         Device(IDEC) {
1353                                 Name(_ADR, 0x00140001)
1354                                 #include "acpi/ide.asl"
1355                         } /* end IDEC */
1356
1357                         Device(AZHD) {
1358                                 Name(_ADR, 0x00140002)
1359                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1360                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1361                                         offset (0x42),
1362                                         NSDI, 1,
1363                                         NSDO, 1,
1364                                         NSEN, 1,
1365                                         offset (0x44),
1366                                         IPCR, 4,
1367                                         offset (0x54),
1368                                         PWST, 2,
1369                                         , 6,
1370                                         PMEB, 1,
1371                                         , 6,
1372                                         PMST, 1,
1373                                         offset (0x62),
1374                                         MMCR, 1,
1375                                         offset (0x64),
1376                                         MMLA, 32,
1377                                         offset (0x68),
1378                                         MMHA, 32,
1379                                         offset (0x6C),
1380                                         MMDT, 16,
1381                                 }
1382
1383                                 Method(_INI) {
1384                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1385                                                 Store(zero, NSEN)
1386                                                 Store(one, NSDO)
1387                                                 Store(one, NSDI)
1388                                         }
1389                                 }
1390                         } /* end AZHD */
1391
1392                         Device(LIBR) {
1393                                 Name(_ADR, 0x00140003)
1394                                 /* Method(_INI) {
1395                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1396                                 } */ /* End Method(_SB.SBRDG._INI) */
1397
1398                                 /* Real Time Clock Device */
1399                                 Device(RTC0) {
1400                                         Name(_HID, EISAID("PNP0B01"))   /* AT Real Time Clock */
1401                                         Name(_CRS, ResourceTemplate() {
1402                                                 IRQNoFlags(){8}
1403                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1404                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1405                                         })
1406                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1407
1408                                 Device(TMR) {   /* Timer */
1409                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1410                                         Name(_CRS, ResourceTemplate() {
1411                                                 IRQNoFlags(){0}
1412                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1413                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1414                                         })
1415                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1416
1417                                 Device(SPKR) {  /* Speaker */
1418                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1419                                         Name(_CRS, ResourceTemplate() {
1420                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1421                                         })
1422                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1423
1424                                 Device(PIC) {
1425                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1426                                         Name(_CRS, ResourceTemplate() {
1427                                                 IRQNoFlags(){2}
1428                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1429                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1430                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1431                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1432                                         })
1433                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1434
1435                                 Device(MAD) { /* 8257 DMA */
1436                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1437                                         Name(_CRS, ResourceTemplate() {
1438                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1439                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1440                                                 IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
1441                                                 IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
1442                                                 IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
1443                                                 IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
1444                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1445                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1446                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1447
1448                                 Device(COPR) {
1449                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1450                                         Name(_CRS, ResourceTemplate() {
1451                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1452                                                 IRQNoFlags(){13}
1453                                         })
1454                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1455 #if 0
1456                                 Device(HPTM) {
1457                                         Name(_HID,EISAID("PNP0103"))
1458                                         Name(CRS,ResourceTemplate()     {
1459                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1460                                         })
1461                                         Method(_STA, 0) {
1462                                                 Return(0x0F) /* sata is visible */
1463                                         }
1464                                         Method(_CRS, 0) {
1465                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1466                                                 Store(HPBA, HPBA)
1467                                                 Return(CRS)
1468                                         }
1469                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1470 #endif
1471                         } /* end LIBR */
1472
1473                         Device(HPBR) {
1474                                 Name(_ADR, 0x00140004)
1475                         } /* end HostPciBr */
1476
1477                         Device(ACAD) {
1478                                 Name(_ADR, 0x00140005)
1479                         } /* end Ac97audio */
1480
1481                         Device(ACMD) {
1482                                 Name(_ADR, 0x00140006)
1483                         } /* end Ac97modem */
1484
1485                         Name(CRES, ResourceTemplate() {
1486                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1487
1488                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1489                                         0x0000,                 /* address granularity */
1490                                         0x0000,                 /* range minimum */
1491                                         0x0CF7,                 /* range maximum */
1492                                         0x0000,                 /* translation */
1493                                         0x0CF8                  /* length */
1494                                 )
1495
1496                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1497                                         0x0000,                 /* address granularity */
1498                                         0x0D00,                 /* range minimum */
1499                                         0xFFFF,                 /* range maximum */
1500                                         0x0000,                 /* translation */
1501                                         0xF300                  /* length */
1502                                 )
1503 #if 0
1504                                 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1505                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1506                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1507                                 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
1508
1509                                 /* DRAM Memory from 1MB to TopMem */
1510                                 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)   /* 1MB to TopMem */
1511
1512                                 /* BIOS space just below 4GB */
1513                                 DWORDMemory(
1514                                         ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1515                                         0x00,                   /* Granularity */
1516                                         0x00000000,             /* Min */
1517                                         0x00000000,             /* Max */
1518                                         0x00000000,             /* Translation */
1519                                         0x00000000,             /* Max-Min, RLEN */
1520                                         ,,
1521                                         PCBM
1522                                 )
1523
1524                                 /* DRAM memory from 4GB to TopMem2 */
1525                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1526                                         0xFFFFFFFF,             /* Granularity */
1527                                         0x00000000,             /*  Min */
1528                                         0x00000000,             /* Max */
1529                                         0x00000000,             /* Translation */
1530                                         0x00000000,             /* Max-Min, RLEN */
1531                                         ,,
1532                                         DMHI
1533                                 )
1534
1535                                 /* BIOS space just below 16EB */
1536                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1537                                         0xFFFFFFFF,             /* Granularity */
1538                                         0x00000000,             /* Min */
1539                                         0x00000000,             /*  Max */
1540                                         0x00000000,             /* Translation */
1541                                         0x00000000,             /* Max-Min, RLEN */
1542                                         ,,
1543                                         PEBM
1544                                 )
1545 #endif
1546                                 /* memory space for PCI BARs below 4GB */
1547                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1548                         }) /* End Name(_SB.PCI0.CRES) */
1549
1550                         Method(_CRS, 0) {
1551                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1552 #if 0
1553                                 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1554                                 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1555                                 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1556                                 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1557                                 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1558                                 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1559
1560                                 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1561                                 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1562                                 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1563                                 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1564
1565                                 If(LGreater(LOMH, 0xC0000)){
1566                                         Store(0xC0000, EM1B)    /* Hole above C0000 and below E0000 */
1567                                         Subtract(LOMH, 0xC0000, EM1L)   /* subtract start, assumes allocation from C0000 going up */
1568                                 }
1569
1570                                 /* Set size of memory from 1MB to TopMem */
1571                                 Subtract(TOM1, 0x100000, DMLL)
1572
1573                                 /*
1574                                 * If(LNotEqual(TOM2, 0x00000000)){
1575                                 *       Store(0x100000000,DMHB)                 DRAM from 4GB to TopMem2
1576                                 *       Subtract(TOM2, 0x100000000, DMHL)
1577                                 * }
1578                                 */
1579
1580                                 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1581                                 If(LEqual(TOM2, 0x00000000)){
1582                                         Store(PBAD,PBMB)                        /* Reserve the "BIOS" space */
1583                                         Store(PBLN,PBML)
1584                                 }
1585                                 Else {  /* Otherwise, put the BIOS just below 16EB */
1586                                         ShiftLeft(PBAD,16,EBMB)         /* Reserve the "BIOS" space */
1587                                         Store(PBLN,EBML)
1588                                 }
1589 #endif
1590                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1591                                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1592                                 /*
1593                                  * Declare memory between TOM1 and 4GB as available
1594                                  * for PCI MMIO.
1595                                  * Use ShiftLeft to avoid 64bit constant (for XP).
1596                                  * This will work even if the OS does 32bit arithmetic, as
1597                                  * 32bit (0x00000000 - TOM1) will wrap and give the same
1598                                  * result as 64bit (0x100000000 - TOM1).
1599                                  */
1600                                 Store(TOM1, MM1B)
1601                                 ShiftLeft(0x10000000, 4, Local0)
1602                                 Subtract(Local0, TOM1, Local0)
1603                                 Store(Local0, MM1L)
1604
1605                                 Return(CRES) /* note to change the Name buffer */
1606                         }  /* end of Method(_SB.PCI0._CRS) */
1607
1608                         /*
1609                         *
1610                         *               FIRST METHOD CALLED UPON BOOT
1611                         *
1612                         *  1. If debugging, print current OS and ACPI interpreter.
1613                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1614                         *     value is based on user choice in BIOS setup.
1615                         */
1616                         Method(_INI, 0) {
1617                                 /* DBGO("\\_SB\\_INI\n") */
1618                                 /* DBGO("   DSDT.ASL code from ") */
1619                                 /* DBGO(__DATE__) */
1620                                 /* DBGO(" ") */
1621                                 /* DBGO(__TIME__) */
1622                                 /* DBGO("\n   Sleep states supported: ") */
1623                                 /* DBGO("\n") */
1624                                 /* DBGO("   \\_OS=") */
1625                                 /* DBGO(\_OS) */
1626                                 /* DBGO("\n   \\_REV=") */
1627                                 /* DBGO(\_REV) */
1628                                 /* DBGO("\n") */
1629
1630                                 /* Determine the OS we're running on */
1631                                 CkOT()
1632
1633                                 /* On older chips, clear PciExpWakeDisEn */
1634                                 /*if (LLessEqual(\SBRI, 0x13)) {
1635                                 *       Store(0,\PWDE)
1636                                 * }
1637                                 */
1638                         } /* End Method(_SB._INI) */
1639                 } /* End Device(PCI0)  */
1640
1641                 Device(PWRB) {  /* Start Power button device */
1642                         Name(_HID, EISAID("PNP0C0C"))
1643                         Name(_UID, 0xAA)
1644                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1645                         Name(_STA, 0x0B) /* sata is invisible */
1646                 }
1647         } /* End \_SB scope */
1648
1649         Scope(\_SI) {
1650                 Method(_SST, 1) {
1651                         /* DBGO("\\_SI\\_SST\n") */
1652                         /* DBGO("   New Indicator state: ") */
1653                         /* DBGO(Arg0) */
1654                         /* DBGO("\n") */
1655                 }
1656         } /* End Scope SI */
1657 #if 0
1658         /* SMBUS Support */
1659         Mutex (SBX0, 0x00)
1660         OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1661                 Field (SMB0, ByteAcc, NoLock, Preserve) {
1662                         HSTS,   8, /* SMBUS status */
1663                         SSTS,   8,  /* SMBUS slave status */
1664                         HCNT,   8,  /* SMBUS control */
1665                         HCMD,   8,  /* SMBUS host cmd */
1666                         HADD,   8,  /* SMBUS address */
1667                         DAT0,   8,  /* SMBUS data0 */
1668                         DAT1,   8,  /* SMBUS data1 */
1669                         BLKD,   8,  /* SMBUS block data */
1670                         SCNT,   8,  /* SMBUS slave control */
1671                         SCMD,   8,  /* SMBUS shaow cmd */
1672                         SEVT,   8,  /* SMBUS slave event */
1673                         SDAT,   8  /* SMBUS slave data */
1674         }
1675
1676         Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1677                 Store (0x1E, HSTS)
1678                 Store (0xFA, Local0)
1679                 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1680                         Stall (0x64)
1681                         Decrement (Local0)
1682                 }
1683
1684                 Return (Local0)
1685         }
1686
1687         Method (SWTC, 1, NotSerialized) {
1688                 Store (Arg0, Local0)
1689                 Store (0x07, Local2)
1690                 Store (One, Local1)
1691                 While (LEqual (Local1, One)) {
1692                         Store (And (HSTS, 0x1E), Local3)
1693                         If (LNotEqual (Local3, Zero)) { /* read sucess */
1694                                 If (LEqual (Local3, 0x02)) {
1695                                         Store (Zero, Local2)
1696                                 }
1697
1698                                 Store (Zero, Local1)
1699                         }
1700                         Else {
1701                                 If (LLess (Local0, 0x0A)) { /* read failure */
1702                                         Store (0x10, Local2)
1703                                         Store (Zero, Local1)
1704                                 }
1705                                 Else {
1706                                         Sleep (0x0A) /* 10 ms, try again */
1707                                         Subtract (Local0, 0x0A, Local0)
1708                                 }
1709                         }
1710                 }
1711
1712                 Return (Local2)
1713         }
1714
1715         Method (SMBR, 3, NotSerialized) {
1716                 Store (0x07, Local0)
1717                 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1718                         Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1719                         If (LEqual (Local0, Zero)) {
1720                                 Release (SBX0)
1721                                 Return (0x0)
1722                         }
1723
1724                         Store (0x1F, HSTS)
1725                         Store (Or (ShiftLeft (Arg1, One), One), HADD)
1726                         Store (Arg2, HCMD)
1727                         If (LEqual (Arg0, 0x07)) {
1728                                 Store (0x48, HCNT) /* read byte */
1729                         }
1730
1731                         Store (SWTC (0x03E8), Local1) /* 1000 ms */
1732                         If (LEqual (Local1, Zero)) {
1733                                 If (LEqual (Arg0, 0x07)) {
1734                                         Store (DAT0, Local0)
1735                                 }
1736                         }
1737                         Else {
1738                                 Store (Local1, Local0)
1739                         }
1740
1741                         Release (SBX0)
1742                 }
1743
1744                 /* DBGO("the value of SMBusData0 register ") */
1745                 /* DBGO(Arg2) */
1746                 /* DBGO(" is ") */
1747                 /* DBGO(Local0) */
1748                 /* DBGO("\n") */
1749
1750                 Return (Local0)
1751         }
1752
1753         /* THERMAL */
1754         Scope(\_TZ) {
1755                 Name (KELV, 2732)
1756                 Name (THOT, 800)
1757                 Name (TCRT, 850)
1758
1759                 ThermalZone(TZ00) {
1760                         Method(_AC0,0) {        /* Active Cooling 0 (0=highest fan speed) */
1761                                 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1762                                 Return(Add(0, 2730))
1763                         }
1764                         Method(_AL0,0) {        /* Returns package of cooling device to turn on */
1765                                 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1766                                 Return(Package() {\_TZ.TZ00.FAN0})
1767                         }
1768                         Device (FAN0) {
1769                                 Name(_HID, EISAID("PNP0C0B"))
1770                                 Name(_PR0, Package() {PFN0})
1771                         }
1772
1773                         PowerResource(PFN0,0,0) {
1774                                 Method(_STA) {
1775                                         Store(0xF,Local0)
1776                                         Return(Local0)
1777                                 }
1778                                 Method(_ON) {
1779                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1780                                 }
1781                                 Method(_OFF) {
1782                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1783                                 }
1784                         }
1785
1786                         Method(_HOT,0) {        /* return hot temp in tenths degree Kelvin */
1787                                 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1788                                 Return (Add (THOT, KELV))
1789                         }
1790                         Method(_CRT,0) {        /* return critical temp in tenths degree Kelvin */
1791                                 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1792                                 Return (Add (TCRT, KELV))
1793                         }
1794                         Method(_TMP,0) {        /* return current temp of this zone */
1795                                 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1796                                 If (LGreater (Local0, 0x10)) {
1797                                         Store (Local0, Local1)
1798                                 }
1799                                 Else {
1800                                         Add (Local0, THOT, Local0)
1801                                         Return (Add (400, KELV))
1802                                 }
1803
1804                                 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1805                                 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1806                                 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1807                                 If (LGreater (Local0, 0x10)) {
1808                                         If (LGreater (Local0, Local1)) {
1809                                                 Store (Local0, Local1)
1810                                         }
1811
1812                                         Multiply (Local1, 10, Local1)
1813                                         Return (Add (Local1, KELV))
1814                                 }
1815                                 Else {
1816                                         Add (Local0, THOT, Local0)
1817                                         Return (Add (400 , KELV))
1818                                 }
1819                         } /* end of _TMP */
1820                 } /* end of TZ00 */
1821         }
1822 #endif
1823 }
1824 /* End of ASL file */