src/mainboard/asus/m5a99x-evo/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",  /* Output filename */
  23         "DSDT",     /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "ASUS    ", /* OEMID */
  26         "M5A99   ",     /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include <arch/x86/acpi/debug.asl> */                /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, 0xE0000000)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* USB overcurrent mapping pins.   */
  45         Name(UOM0, 0)
  46         Name(UOM1, 2)
  47         Name(UOM2, 0)
  48         Name(UOM3, 7)
  49         Name(UOM4, 2)
  50         Name(UOM5, 2)
  51         Name(UOM6, 6)
  52         Name(UOM7, 2)
  53         Name(UOM8, 6)
  54         Name(UOM9, 6)
  55
  56         /* Some global data */
  57         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
  58         Name(OSV, Ones) /* Assume nothing */
  59         Name(PMOD, One) /* Assume APIC */
  60
  61         /*
  62          * Processor Object
  63          *
  64          */
  65         Scope (\_PR) {          /* define processor scope */
  66                 Processor(
  67                         CPU0,           /* name space name */
  68                         0,              /* Unique number for this processor */
  69                         0x808,          /* PBLK system I/O address !hardcoded! */
  70                         0x06            /* PBLKLEN for boot processor */
  71                         ) {
  72                         #include "acpi/cpstate.asl"
  73                 }
  74
  75                 Processor(
  76                         CPU1,           /* name space name */
  77                         1,              /* Unique number for this processor */
  78                         0x0000,         /* PBLK system I/O address !hardcoded! */
  79                         0x00            /* PBLKLEN for boot processor */
  80                         ) {
  81                         #include "acpi/cpstate.asl"
  82                 }
  83
  84                 Processor(
  85                         CPU2,           /* name space name */
  86                         2,              /* Unique number for this processor */
  87                         0x0000,         /* PBLK system I/O address !hardcoded! */
  88                         0x00            /* PBLKLEN for boot processor */
  89                         ) {
  90                         #include "acpi/cpstate.asl"
  91                 }
  92
  93                 Processor(
  94                         CPU3,           /* name space name */
  95                         3,              /* Unique number for this processor */
  96                         0x0000,         /* PBLK system I/O address !hardcoded! */
  97                         0x00            /* PBLKLEN for boot processor */
  98                         ) {
  99                         #include "acpi/cpstate.asl"
 100                 }
 101
 102                 Processor(
 103                         CPU4,           /* name space name */
 104                         4,              /* Unique number for this processor */
 105                         0x0000,         /* PBLK system I/O address !hardcoded! */
 106                         0x00            /* PBLKLEN for boot processor */
 107                         ) {
 108                         #include "acpi/cpstate.asl"
 109                 }
 110
 111                 Processor(
 112                         CPU5,           /* name space name */
 113                         5,              /* Unique number for this processor */
 114                         0x0000,         /* PBLK system I/O address !hardcoded! */
 115                         0x00            /* PBLKLEN for boot processor */
 116                         ) {
 117                         #include "acpi/cpstate.asl"
 118                 }
 119         } /* End _PR scope */
 120
 121         /* PIC IRQ mapping registers, C00h-C01h */
 122         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 123                 Field(PRQM, ByteAcc, NoLock, Preserve) {
 124                 PRQI, 0x00000008,
 125                 PRQD, 0x00000008,  /* Offset: 1h */
 126         }
 127         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 128                 PINA, 0x00000008,       /* Index 0  */
 129                 PINB, 0x00000008,       /* Index 1 */
 130                 PINC, 0x00000008,       /* Index 2 */
 131                 PIND, 0x00000008,       /* Index 3 */
 132                 AINT, 0x00000008,       /* Index 4 */
 133                 SINT, 0x00000008,       /*  Index 5 */
 134                 , 0x00000008,                /* Index 6 */
 135                 AAUD, 0x00000008,       /* Index 7 */
 136                 AMOD, 0x00000008,       /* Index 8 */
 137                 PINE, 0x00000008,       /* Index 9 */
 138                 PINF, 0x00000008,       /* Index A */
 139                 PING, 0x00000008,       /* Index B */
 140                 PINH, 0x00000008,       /* Index C */
 141         }
 142
 143         /* PCI Error control register */
 144         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 145                 Field(PERC, ByteAcc, NoLock, Preserve) {
 146                 SENS, 0x00000001,
 147                 PENS, 0x00000001,
 148                 SENE, 0x00000001,
 149                 PENE, 0x00000001,
 150         }
 151
 152         /* Client Management index/data registers */
 153         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 154                 Field(CMT, ByteAcc, NoLock, Preserve) {
 155                 CMTI,      8,
 156                 /* Client Management Data register */
 157                 G64E,   1,
 158                 G64O,      1,
 159                 G32O,      2,
 160                 ,       2,
 161                 GPSL,     2,
 162         }
 163
 164         /* GPM Port register */
 165         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 166                 Field(GPT, ByteAcc, NoLock, Preserve) {
 167                 GPB0,1,
 168                 GPB1,1,
 169                 GPB2,1,
 170                 GPB3,1,
 171                 GPB4,1,
 172                 GPB5,1,
 173                 GPB6,1,
 174                 GPB7,1,
 175         }
 176
 177         /* Flash ROM program enable register */
 178         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 179                 Field(FRE, ByteAcc, NoLock, Preserve) {
 180                 ,     0x00000006,
 181                 FLRE, 0x00000001,
 182         }
 183
 184         /* PM2 index/data registers */
 185         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 186                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 187                 PM2I, 0x00000008,
 188                 PM2D, 0x00000008,
 189         }
 190
 191         /* Power Management I/O registers */
 192         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 193                 Field(PIOR, ByteAcc, NoLock, Preserve) {
 194                 PIOI, 0x00000008,
 195                 PIOD, 0x00000008,
 196         }
 197         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 198                 Offset(0x00),   /* MiscControl */
 199                 , 1,
 200                 T1EE, 1,
 201                 T2EE, 1,
 202                 Offset(0x01),   /* MiscStatus */
 203                 , 1,
 204                 T1E, 1,
 205                 T2E, 1,
 206                 Offset(0x04),   /* SmiWakeUpEventEnable3 */
 207                 , 7,
 208                 SSEN, 1,
 209                 Offset(0x07),   /* SmiWakeUpEventStatus3 */
 210                 , 7,
 211                 CSSM, 1,
 212                 Offset(0x10),   /* AcpiEnable */
 213                 , 6,
 214                 PWDE, 1,
 215                 Offset(0x1C),   /* ProgramIoEnable */
 216                 , 3,
 217                 MKME, 1,
 218                 IO3E, 1,
 219                 IO2E, 1,
 220                 IO1E, 1,
 221                 IO0E, 1,
 222                 Offset(0x1D),   /* IOMonitorStatus */
 223                 , 3,
 224                 MKMS, 1,
 225                 IO3S, 1,
 226                 IO2S, 1,
 227                 IO1S, 1,
 228                 IO0S,1,
 229                 Offset(0x20),   /* AcpiPmEvtBlk */
 230                 APEB, 16,
 231                 Offset(0x36),   /* GEvtLevelConfig */
 232                 , 6,
 233                 ELC6, 1,
 234                 ELC7, 1,
 235                 Offset(0x37),   /* GPMLevelConfig0 */
 236                 , 3,
 237                 PLC0, 1,
 238                 PLC1, 1,
 239                 PLC2, 1,
 240                 PLC3, 1,
 241                 PLC8, 1,
 242                 Offset(0x38),   /* GPMLevelConfig1 */
 243                 , 1,
 244                  PLC4, 1,
 245                  PLC5, 1,
 246                 , 1,
 247                  PLC6, 1,
 248                  PLC7, 1,
 249                 Offset(0x3B),   /* PMEStatus1 */
 250                 GP0S, 1,
 251                 GM4S, 1,
 252                 GM5S, 1,
 253                 APS, 1,
 254                 GM6S, 1,
 255                 GM7S, 1,
 256                 GP2S, 1,
 257                 STSS, 1,
 258                 Offset(0x55),   /* SoftPciRst */
 259                 SPRE, 1,
 260                 , 1,
 261                 , 1,
 262                 PNAT, 1,
 263                 PWMK, 1,
 264                 PWNS, 1,
 265
 266                 /*      Offset(0x61), */        /*  Options_1 */
 267                 /*              ,7,  */
 268                 /*              R617,1, */
 269
 270                 Offset(0x65),   /* UsbPMControl */
 271                 , 4,
 272                 URRE, 1,
 273                 Offset(0x68),   /* MiscEnable68 */
 274                 , 3,
 275                 TMTE, 1,
 276                 , 1,
 277                 Offset(0x92),   /* GEVENTIN */
 278                 , 7,
 279                 E7IS, 1,
 280                 Offset(0x96),   /* GPM98IN */
 281                 G8IS, 1,
 282                 G9IS, 1,
 283                 Offset(0x9A),   /* EnhanceControl */
 284                 ,7,
 285                 HPDE, 1,
 286                 Offset(0xA8),   /* PIO7654Enable */
 287                 IO4E, 1,
 288                 IO5E, 1,
 289                 IO6E, 1,
 290                 IO7E, 1,
 291                 Offset(0xA9),   /* PIO7654Status */
 292                 IO4S, 1,
 293                 IO5S, 1,
 294                 IO6S, 1,
 295                 IO7S, 1,
 296         }
 297
 298         /* PM1 Event Block
 299         * First word is PM1_Status, Second word is PM1_Enable
 300         */
 301         OperationRegion(P1EB, SystemIO, APEB, 0x04)
 302                 Field(P1EB, ByteAcc, NoLock, Preserve) {
 303                 TMST, 1,
 304                 ,    3,
 305                 BMST,    1,
 306                 GBST,   1,
 307                 Offset(0x01),
 308                 PBST, 1,
 309                 , 1,
 310                 RTST, 1,
 311                 , 3,
 312                 PWST, 1,
 313                 SPWS, 1,
 314                 Offset(0x02),
 315                 TMEN, 1,
 316                 , 4,
 317                 GBEN, 1,
 318                 Offset(0x03),
 319                 PBEN, 1,
 320                 , 1,
 321                 RTEN, 1,
 322                 , 3,
 323                 PWDA, 1,
 324         }
 325
 326         Scope(\_SB) {
 327                 /* PCIe Configuration Space for 16 busses */
 328                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 329                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 330                         /* Byte offsets are computed using the following technique:
 331                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 332                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 333                         */
 334                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 335                         STB5, 32,
 336                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 337                         PT0D, 1,
 338                         PT1D, 1,
 339                         PT2D, 1,
 340                         PT3D, 1,
 341                         PT4D, 1,
 342                         PT5D, 1,
 343                         PT6D, 1,
 344                         PT7D, 1,
 345                         PT8D, 1,
 346                         PT9D, 1,
 347                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 348                         SBIE, 1,
 349                         SBME, 1,
 350                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 351                         SBRI, 8,
 352                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 353                         SBB1, 32,
 354                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 355                         ,14,
 356                         P92E, 1,                /* Port92 decode enable */
 357                 }
 358
 359                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 360                         Field(SB5, AnyAcc, NoLock, Preserve){
 361                         /* Port 0 */
 362                         Offset(0x120),          /* Port 0 Task file status */
 363                         P0ER, 1,
 364                         , 2,
 365                         P0DQ, 1,
 366                         , 3,
 367                         P0BY, 1,
 368                         Offset(0x128),          /* Port 0 Serial ATA status */
 369                         P0DD, 4,
 370                         , 4,
 371                         P0IS, 4,
 372                         Offset(0x12C),          /* Port 0 Serial ATA control */
 373                         P0DI, 4,
 374                         Offset(0x130),          /* Port 0 Serial ATA error */
 375                         , 16,
 376                         P0PR, 1,
 377
 378                         /* Port 1 */
 379                         offset(0x1A0),          /* Port 1 Task file status */
 380                         P1ER, 1,
 381                         , 2,
 382                         P1DQ, 1,
 383                         , 3,
 384                         P1BY, 1,
 385                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 386                         P1DD, 4,
 387                         , 4,
 388                         P1IS, 4,
 389                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 390                         P1DI, 4,
 391                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 392                         , 16,
 393                         P1PR, 1,
 394
 395                         /* Port 2 */
 396                         Offset(0x220),          /* Port 2 Task file status */
 397                         P2ER, 1,
 398                         , 2,
 399                         P2DQ, 1,
 400                         , 3,
 401                         P2BY, 1,
 402                         Offset(0x228),          /* Port 2 Serial ATA status */
 403                         P2DD, 4,
 404                         , 4,
 405                         P2IS, 4,
 406                         Offset(0x22C),          /* Port 2 Serial ATA control */
 407                         P2DI, 4,
 408                         Offset(0x230),          /* Port 2 Serial ATA error */
 409                         , 16,
 410                         P2PR, 1,
 411
 412                         /* Port 3 */
 413                         Offset(0x2A0),          /* Port 3 Task file status */
 414                         P3ER, 1,
 415                         , 2,
 416                         P3DQ, 1,
 417                         , 3,
 418                         P3BY, 1,
 419                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 420                         P3DD, 4,
 421                         , 4,
 422                         P3IS, 4,
 423                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 424                         P3DI, 4,
 425                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 426                         , 16,
 427                         P3PR, 1,
 428                 }
 429         }
 430
 431
 432         #include "acpi/routing.asl"
 433
 434         Scope(\_SB) {
 435
 436                 Method(CkOT, 0){
 437
 438                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
 439
 440                         if(CondRefOf(\_OSI,Local1))
 441                         {
 442                                 Store(1, OSTP)                /* Assume some form of XP */
 443                                 if (\_OSI("Windows 2006"))      /* Vista */
 444                                 {
 445                                         Store(2, OSTP)
 446                                 }
 447                         } else {
 448                                 If(WCMP(\_OS,"Linux")) {
 449                                         Store(3, OSTP)            /* Linux */
 450                                 } Else {
 451                                         Store(4, OSTP)            /* Gotta be WinCE */
 452                                 }
 453                         }
 454                         Return(OSTP)
 455                 }
 456
 457                 Method(_PIC, 0x01, NotSerialized)
 458                 {
 459                         If (Arg0)
 460                         {
 461                                 \_SB.CIRQ()
 462                         }
 463                         Store(Arg0, PMOD)
 464                 }
 465                 Method(CIRQ, 0x00, NotSerialized){
 466                         Store(0, PINA)
 467                         Store(0, PINB)
 468                         Store(0, PINC)
 469                         Store(0, PIND)
 470                         Store(0, PINE)
 471                         Store(0, PINF)
 472                         Store(0, PING)
 473                         Store(0, PINH)
 474                 }
 475
 476                 Name(IRQB, ResourceTemplate(){
 477                         IRQ(Level,ActiveLow,Shared){15}
 478                 })
 479
 480                 Name(IRQP, ResourceTemplate(){
 481                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
 482                 })
 483
 484                 Name(PITF, ResourceTemplate(){
 485                         IRQ(Level,ActiveLow,Exclusive){9}
 486                 })
 487
 488                 Device(INTA) {
 489                         Name(_HID, EISAID("PNP0C0F"))
 490                         Name(_UID, 1)
 491
 492                         Method(_STA, 0) {
 493                                 if (PINA) {
 494                                         Return(0x0B) /* sata is invisible */
 495                                 } else {
 496                                         Return(0x09) /* sata is disabled */
 497                                 }
 498                         } /* End Method(_SB.INTA._STA) */
 499
 500                         Method(_DIS ,0) {
 501                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
 502                                 Store(0, PINA)
 503                         } /* End Method(_SB.INTA._DIS) */
 504
 505                         Method(_PRS ,0) {
 506                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
 507                                 Return(IRQP)
 508                         } /* Method(_SB.INTA._PRS) */
 509
 510                         Method(_CRS ,0) {
 511                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 512                                 CreateWordField(IRQB, 0x1, IRQN)
 513                                 ShiftLeft(1, PINA, IRQN)
 514                                 Return(IRQB)
 515                         } /* Method(_SB.INTA._CRS) */
 516
 517                         Method(_SRS, 1) {
 518                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 519                                 CreateWordField(ARG0, 1, IRQM)
 520
 521                                 /* Use lowest available IRQ */
 522                                 FindSetRightBit(IRQM, Local0)
 523                                 if (Local0) {
 524                                         Decrement(Local0)
 525                                 }
 526                                 Store(Local0, PINA)
 527                         } /* End Method(_SB.INTA._SRS) */
 528                 } /* End Device(INTA) */
 529
 530                 Device(INTB) {
 531                         Name(_HID, EISAID("PNP0C0F"))
 532                         Name(_UID, 2)
 533
 534                         Method(_STA, 0) {
 535                                 if (PINB) {
 536                                         Return(0x0B) /* sata is invisible */
 537                                 } else {
 538                                         Return(0x09) /* sata is disabled */
 539                                 }
 540                         } /* End Method(_SB.INTB._STA) */
 541
 542                         Method(_DIS ,0) {
 543                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
 544                                 Store(0, PINB)
 545                         } /* End Method(_SB.INTB._DIS) */
 546
 547                         Method(_PRS ,0) {
 548                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
 549                                 Return(IRQP)
 550                         } /* Method(_SB.INTB._PRS) */
 551
 552                         Method(_CRS ,0) {
 553                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 554                                 CreateWordField(IRQB, 0x1, IRQN)
 555                                 ShiftLeft(1, PINB, IRQN)
 556                                 Return(IRQB)
 557                         } /* Method(_SB.INTB._CRS) */
 558
 559                         Method(_SRS, 1) {
 560                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 561                                 CreateWordField(ARG0, 1, IRQM)
 562
 563                                 /* Use lowest available IRQ */
 564                                 FindSetRightBit(IRQM, Local0)
 565                                 if (Local0) {
 566                                         Decrement(Local0)
 567                                 }
 568                                 Store(Local0, PINB)
 569                         } /* End Method(_SB.INTB._SRS) */
 570                 } /* End Device(INTB)  */
 571
 572                 Device(INTC) {
 573                         Name(_HID, EISAID("PNP0C0F"))
 574                         Name(_UID, 3)
 575
 576                         Method(_STA, 0) {
 577                                 if (PINC) {
 578                                         Return(0x0B) /* sata is invisible */
 579                                 } else {
 580                                         Return(0x09) /* sata is disabled */
 581                                 }
 582                         } /* End Method(_SB.INTC._STA) */
 583
 584                         Method(_DIS ,0) {
 585                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
 586                                 Store(0, PINC)
 587                         } /* End Method(_SB.INTC._DIS) */
 588
 589                         Method(_PRS ,0) {
 590                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
 591                                 Return(IRQP)
 592                         } /* Method(_SB.INTC._PRS) */
 593
 594                         Method(_CRS ,0) {
 595                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 596                                 CreateWordField(IRQB, 0x1, IRQN)
 597                                 ShiftLeft(1, PINC, IRQN)
 598                                 Return(IRQB)
 599                         } /* Method(_SB.INTC._CRS) */
 600
 601                         Method(_SRS, 1) {
 602                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 603                                 CreateWordField(ARG0, 1, IRQM)
 604
 605                                 /* Use lowest available IRQ */
 606                                 FindSetRightBit(IRQM, Local0)
 607                                 if (Local0) {
 608                                         Decrement(Local0)
 609                                 }
 610                                 Store(Local0, PINC)
 611                         } /* End Method(_SB.INTC._SRS) */
 612                 } /* End Device(INTC)  */
 613
 614                 Device(INTD) {
 615                         Name(_HID, EISAID("PNP0C0F"))
 616                         Name(_UID, 4)
 617
 618                         Method(_STA, 0) {
 619                                 if (PIND) {
 620                                         Return(0x0B) /* sata is invisible */
 621                                 } else {
 622                                         Return(0x09) /* sata is disabled */
 623                                 }
 624                         } /* End Method(_SB.INTD._STA) */
 625
 626                         Method(_DIS ,0) {
 627                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
 628                                 Store(0, PIND)
 629                         } /* End Method(_SB.INTD._DIS) */
 630
 631                         Method(_PRS ,0) {
 632                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
 633                                 Return(IRQP)
 634                         } /* Method(_SB.INTD._PRS) */
 635
 636                         Method(_CRS ,0) {
 637                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 638                                 CreateWordField(IRQB, 0x1, IRQN)
 639                                 ShiftLeft(1, PIND, IRQN)
 640                                 Return(IRQB)
 641                         } /* Method(_SB.INTD._CRS) */
 642
 643                         Method(_SRS, 1) {
 644                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 645                                 CreateWordField(ARG0, 1, IRQM)
 646
 647                                 /* Use lowest available IRQ */
 648                                 FindSetRightBit(IRQM, Local0)
 649                                 if (Local0) {
 650                                         Decrement(Local0)
 651                                 }
 652                                 Store(Local0, PIND)
 653                         } /* End Method(_SB.INTD._SRS) */
 654                 } /* End Device(INTD)  */
 655
 656                 Device(INTE) {
 657                         Name(_HID, EISAID("PNP0C0F"))
 658                         Name(_UID, 5)
 659
 660                         Method(_STA, 0) {
 661                                 if (PINE) {
 662                                         Return(0x0B) /* sata is invisible */
 663                                 } else {
 664                                         Return(0x09) /* sata is disabled */
 665                                 }
 666                         } /* End Method(_SB.INTE._STA) */
 667
 668                         Method(_DIS ,0) {
 669                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
 670                                 Store(0, PINE)
 671                         } /* End Method(_SB.INTE._DIS) */
 672
 673                         Method(_PRS ,0) {
 674                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
 675                                 Return(IRQP)
 676                         } /* Method(_SB.INTE._PRS) */
 677
 678                         Method(_CRS ,0) {
 679                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 680                                 CreateWordField(IRQB, 0x1, IRQN)
 681                                 ShiftLeft(1, PINE, IRQN)
 682                                 Return(IRQB)
 683                         } /* Method(_SB.INTE._CRS) */
 684
 685                         Method(_SRS, 1) {
 686                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 687                                 CreateWordField(ARG0, 1, IRQM)
 688
 689                                 /* Use lowest available IRQ */
 690                                 FindSetRightBit(IRQM, Local0)
 691                                 if (Local0) {
 692                                         Decrement(Local0)
 693                                 }
 694                                 Store(Local0, PINE)
 695                         } /* End Method(_SB.INTE._SRS) */
 696                 } /* End Device(INTE)  */
 697
 698                 Device(INTF) {
 699                         Name(_HID, EISAID("PNP0C0F"))
 700                         Name(_UID, 6)
 701
 702                         Method(_STA, 0) {
 703                                 if (PINF) {
 704                                         Return(0x0B) /* sata is invisible */
 705                                 } else {
 706                                         Return(0x09) /* sata is disabled */
 707                                 }
 708                         } /* End Method(_SB.INTF._STA) */
 709
 710                         Method(_DIS ,0) {
 711                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
 712                                 Store(0, PINF)
 713                         } /* End Method(_SB.INTF._DIS) */
 714
 715                         Method(_PRS ,0) {
 716                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
 717                                 Return(PITF)
 718                         } /* Method(_SB.INTF._PRS) */
 719
 720                         Method(_CRS ,0) {
 721                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 722                                 CreateWordField(IRQB, 0x1, IRQN)
 723                                 ShiftLeft(1, PINF, IRQN)
 724                                 Return(IRQB)
 725                         } /* Method(_SB.INTF._CRS) */
 726
 727                         Method(_SRS, 1) {
 728                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 729                                 CreateWordField(ARG0, 1, IRQM)
 730
 731                                 /* Use lowest available IRQ */
 732                                 FindSetRightBit(IRQM, Local0)
 733                                 if (Local0) {
 734                                         Decrement(Local0)
 735                                 }
 736                                 Store(Local0, PINF)
 737                         } /*  End Method(_SB.INTF._SRS) */
 738                 } /* End Device(INTF)  */
 739
 740                 Device(INTG) {
 741                         Name(_HID, EISAID("PNP0C0F"))
 742                         Name(_UID, 7)
 743
 744                         Method(_STA, 0) {
 745                                 if (PING) {
 746                                         Return(0x0B) /* sata is invisible */
 747                                 } else {
 748                                         Return(0x09) /* sata is disabled */
 749                                 }
 750                         } /* End Method(_SB.INTG._STA)  */
 751
 752                         Method(_DIS ,0) {
 753                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
 754                                 Store(0, PING)
 755                         } /* End Method(_SB.INTG._DIS)  */
 756
 757                         Method(_PRS ,0) {
 758                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
 759                                 Return(IRQP)
 760                         } /* Method(_SB.INTG._CRS)  */
 761
 762                         Method(_CRS ,0) {
 763                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 764                                 CreateWordField(IRQB, 0x1, IRQN)
 765                                 ShiftLeft(1, PING, IRQN)
 766                                 Return(IRQB)
 767                         } /* Method(_SB.INTG._CRS)  */
 768
 769                         Method(_SRS, 1) {
 770                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 771                                 CreateWordField(ARG0, 1, IRQM)
 772
 773                                 /* Use lowest available IRQ */
 774                                 FindSetRightBit(IRQM, Local0)
 775                                 if (Local0) {
 776                                         Decrement(Local0)
 777                                 }
 778                                 Store(Local0, PING)
 779                         } /* End Method(_SB.INTG._SRS)  */
 780                 } /* End Device(INTG)  */
 781
 782                 Device(INTH) {
 783                         Name(_HID, EISAID("PNP0C0F"))
 784                         Name(_UID, 8)
 785
 786                         Method(_STA, 0) {
 787                                 if (PINH) {
 788                                         Return(0x0B) /* sata is invisible */
 789                                 } else {
 790                                         Return(0x09) /* sata is disabled */
 791                                 }
 792                         } /* End Method(_SB.INTH._STA)  */
 793
 794                         Method(_DIS ,0) {
 795                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
 796                                 Store(0, PINH)
 797                         } /* End Method(_SB.INTH._DIS)  */
 798
 799                         Method(_PRS ,0) {
 800                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
 801                                 Return(IRQP)
 802                         } /* Method(_SB.INTH._CRS)  */
 803
 804                         Method(_CRS ,0) {
 805                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 806                                 CreateWordField(IRQB, 0x1, IRQN)
 807                                 ShiftLeft(1, PINH, IRQN)
 808                                 Return(IRQB)
 809                         } /* Method(_SB.INTH._CRS)  */
 810
 811                         Method(_SRS, 1) {
 812                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 813                                 CreateWordField(ARG0, 1, IRQM)
 814
 815                                 /* Use lowest available IRQ */
 816                                 FindSetRightBit(IRQM, Local0)
 817                                 if (Local0) {
 818                                         Decrement(Local0)
 819                                 }
 820                                 Store(Local0, PINH)
 821                         } /* End Method(_SB.INTH._SRS)  */
 822                 } /* End Device(INTH)   */
 823
 824         }   /* End Scope(_SB)  */
 825
 826
 827         /* Supported sleep states: */
 828         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 829
 830         If (LAnd(SSFG, 0x01)) {
 831                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 832         }
 833         If (LAnd(SSFG, 0x02)) {
 834                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 835         }
 836         If (LAnd(SSFG, 0x04)) {
 837                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 838         }
 839         If (LAnd(SSFG, 0x08)) {
 840                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 841         }
 842
 843         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 844
 845         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 846         Name(CSMS, 0)                   /* Current System State */
 847
 848         /* Wake status package */
 849         Name(WKST,Package(){Zero, Zero})
 850
 851         /*
 852         * \_PTS - Prepare to Sleep method
 853         *
 854         *       Entry:
 855         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 856         *
 857         * Exit:
 858         *               -none-
 859         *
 860         * The _PTS control method is executed at the beginning of the sleep process
 861         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 862         * control method may be executed a relatively long time before entering the
 863         * sleep state and the OS may abort      the operation without notification to
 864         * the ACPI driver.  This method cannot modify the configuration or power
 865         * state of any device in the system.
 866         */
 867         Method(\_PTS, 1) {
 868                 /* DBGO("\\_PTS\n") */
 869                 /* DBGO("From S0 to S") */
 870                 /* DBGO(Arg0) */
 871                 /* DBGO("\n") */
 872
 873                 /* Don't allow PCIRST# to reset USB */
 874                 if (LEqual(Arg0,3)){
 875                         Store(0,URRE)
 876                 }
 877
 878                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 879                 /*Store(One, CSSM)
 880                 Store(One, SSEN)*/
 881
 882                 /* On older chips, clear PciExpWakeDisEn */
 883                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 884                 *       Store(0,\_SB.PWDE)
 885                 *}
 886                 */
 887
 888                 /* Clear wake status structure. */
 889                 Store(0, Index(WKST,0))
 890                 Store(0, Index(WKST,1))
 891                 \_SB.PCI0.SIOS (Arg0)
 892         } /* End Method(\_PTS) */
 893
 894         /*
 895         *  The following method results in a "not a valid reserved NameSeg"
 896         *  warning so I have commented it out for the duration.  It isn't
 897         *  used, so it could be removed.
 898         *
 899         *
 900         *       \_GTS OEM Going To Sleep method
 901         *
 902         *       Entry:
 903         *               Arg0=The value of the sleeping state S1=1, S2=2
 904         *
 905         *       Exit:
 906         *               -none-
 907         *
 908         *  Method(\_GTS, 1) {
 909         *  DBGO("\\_GTS\n")
 910         *  DBGO("From S0 to S")
 911         *  DBGO(Arg0)
 912         *  DBGO("\n")
 913         *  }
 914         */
 915
 916         /*
 917         *       \_BFS OEM Back From Sleep method
 918         *
 919         *       Entry:
 920         *               Arg0=The value of the sleeping state S1=1, S2=2
 921         *
 922         *       Exit:
 923         *               -none-
 924         */
 925         Method(\_BFS, 1) {
 926                 /* DBGO("\\_BFS\n") */
 927                 /* DBGO("From S") */
 928                 /* DBGO(Arg0) */
 929                 /* DBGO(" to S0\n") */
 930         }
 931
 932         /*
 933         *  \_WAK System Wake method
 934         *
 935         *       Entry:
 936         *               Arg0=The value of the sleeping state S1=1, S2=2
 937         *
 938         *       Exit:
 939         *               Return package of 2 DWords
 940         *               Dword 1 - Status
 941         *                       0x00000000      wake succeeded
 942         *                       0x00000001      Wake was signaled but failed due to lack of power
 943         *                       0x00000002      Wake was signaled but failed due to thermal condition
 944         *               Dword 2 - Power Supply state
 945         *                       if non-zero the effective S-state the power supply entered
 946         */
 947         Method(\_WAK, 1) {
 948                 /* DBGO("\\_WAK\n") */
 949                 /* DBGO("From S") */
 950                 /* DBGO(Arg0) */
 951                 /* DBGO(" to S0\n") */
 952
 953                 /* Re-enable HPET */
 954                 Store(1,HPDE)
 955
 956                 /* Restore PCIRST# so it resets USB */
 957                 if (LEqual(Arg0,3)){
 958                         Store(1,URRE)
 959                 }
 960
 961                 /* Arbitrarily clear PciExpWakeStatus */
 962                 Store(PWST, PWST)
 963
 964                 /* if(DeRefOf(Index(WKST,0))) {
 965                 *       Store(0, Index(WKST,1))
 966                 * } else {
 967                 *       Store(Arg0, Index(WKST,1))
 968                 * }
 969                 */
 970                 \_SB.PCI0.SIOW (Arg0)
 971                 Return(WKST)
 972         } /* End Method(\_WAK) */
 973
 974         Scope(\_GPE) {  /* Start Scope GPE */
 975                 /*  General event 0  */
 976                 /* Method(_L00) {
 977                 *       DBGO("\\_GPE\\_L00\n")
 978                 * }
 979                 */
 980
 981                 /*  General event 1  */
 982                 /* Method(_L01) {
 983                 *       DBGO("\\_GPE\\_L00\n")
 984                 * }
 985                 */
 986
 987                 /*  General event 2  */
 988                 /* Method(_L02) {
 989                 *       DBGO("\\_GPE\\_L00\n")
 990                 * }
 991                 */
 992
 993                 /*  General event 3  */
 994                 Method(_L03) {
 995                         /* DBGO("\\_GPE\\_L00\n") */
 996                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 997                 }
 998
 999                 /*  General event 4  */
1000                 /* Method(_L04) {
1001                 *       DBGO("\\_GPE\\_L00\n")
1002                 * }
1003                 */
1004
1005                 /*  General event 5  */
1006                 /* Method(_L05) {
1007                 *       DBGO("\\_GPE\\_L00\n")
1008                 * }
1009                 */
1010
1011                 /*  General event 6 - Used for GPM6, moved to USB.asl */
1012                 /* Method(_L06) {
1013                 *       DBGO("\\_GPE\\_L00\n")
1014                 * }
1015                 */
1016
1017                 /*  General event 7 - Used for GPM7, moved to USB.asl */
1018                 /* Method(_L07) {
1019                 *       DBGO("\\_GPE\\_L07\n")
1020                 * }
1021                 */
1022
1023                 /*  Legacy PM event  */
1024                 Method(_L08) {
1025                         /* DBGO("\\_GPE\\_L08\n") */
1026                 }
1027
1028                 /*  Temp warning (TWarn) event  */
1029                 Method(_L09) {
1030                         /* DBGO("\\_GPE\\_L09\n") */
1031                         Notify (\_TZ.TZ00, 0x80)
1032                 }
1033
1034                 /*  Reserved  */
1035                 /* Method(_L0A) {
1036                 *       DBGO("\\_GPE\\_L0A\n")
1037                 * }
1038                 */
1039
1040                 /*  USB controller PME#  */
1041                 Method(_L0B) {
1042                         /* DBGO("\\_GPE\\_L0B\n") */
1043                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1044                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1045                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1046                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1047                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1048                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1049                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1050                 }
1051
1052                 /*  AC97 controller PME#  */
1053                 /* Method(_L0C) {
1054                 *       DBGO("\\_GPE\\_L0C\n")
1055                 * }
1056                 */
1057
1058                 /*  OtherTherm PME#  */
1059                 /* Method(_L0D) {
1060                 *       DBGO("\\_GPE\\_L0D\n")
1061                 * }
1062                 */
1063
1064                 /*  GPM9 SCI event - Moved to USB.asl */
1065                 /* Method(_L0E) {
1066                 *       DBGO("\\_GPE\\_L0E\n")
1067                 * }
1068                 */
1069
1070                 /*  PCIe HotPlug event  */
1071                 /* Method(_L0F) {
1072                 *       DBGO("\\_GPE\\_L0F\n")
1073                 * }
1074                 */
1075
1076                 /*  ExtEvent0 SCI event  */
1077                 Method(_L10) {
1078                         /* DBGO("\\_GPE\\_L10\n") */
1079                 }
1080
1081
1082                 /*  ExtEvent1 SCI event  */
1083                 Method(_L11) {
1084                         /* DBGO("\\_GPE\\_L11\n") */
1085                 }
1086
1087                 /*  PCIe PME# event  */
1088                 /* Method(_L12) {
1089                 *       DBGO("\\_GPE\\_L12\n")
1090                 * }
1091                 */
1092
1093                 /*  GPM0 SCI event - Moved to USB.asl */
1094                 /* Method(_L13) {
1095                 *       DBGO("\\_GPE\\_L13\n")
1096                 * }
1097                 */
1098
1099                 /*  GPM1 SCI event - Moved to USB.asl */
1100                 /* Method(_L14) {
1101                 *       DBGO("\\_GPE\\_L14\n")
1102                 * }
1103                 */
1104
1105                 /*  GPM2 SCI event - Moved to USB.asl */
1106                 /* Method(_L15) {
1107                 *       DBGO("\\_GPE\\_L15\n")
1108                 * }
1109                 */
1110
1111                 /*  GPM3 SCI event - Moved to USB.asl */
1112                 /* Method(_L16) {
1113                 *       DBGO("\\_GPE\\_L16\n")
1114                 * }
1115                 */
1116
1117                 /*  GPM8 SCI event - Moved to USB.asl */
1118                 /* Method(_L17) {
1119                 *       DBGO("\\_GPE\\_L17\n")
1120                 * }
1121                 */
1122
1123                 /*  GPIO0 or GEvent8 event  */
1124                 Method(_L18) {
1125                         /* DBGO("\\_GPE\\_L18\n") */
1126                         Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1127                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1128                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1129                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1130                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1131                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1132                 }
1133
1134                 /*  GPM4 SCI event - Moved to USB.asl */
1135                 /* Method(_L19) {
1136                 *       DBGO("\\_GPE\\_L19\n")
1137                 * }
1138                 */
1139
1140                 /*  GPM5 SCI event - Moved to USB.asl */
1141                 /* Method(_L1A) {
1142                 *       DBGO("\\_GPE\\_L1A\n")
1143                 * }
1144                 */
1145
1146                 /*  Azalia SCI event  */
1147                 Method(_L1B) {
1148                         /* DBGO("\\_GPE\\_L1B\n") */
1149                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1150                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1151                 }
1152
1153                 /*  GPM6 SCI event - Reassigned to _L06 */
1154                 /* Method(_L1C) {
1155                 *       DBGO("\\_GPE\\_L1C\n")
1156                 * }
1157                 */
1158
1159                 /*  GPM7 SCI event - Reassigned to _L07 */
1160                 /* Method(_L1D) {
1161                 *       DBGO("\\_GPE\\_L1D\n")
1162                 * }
1163                 */
1164
1165                 /*  GPIO2 or GPIO66 SCI event  */
1166                 /* Method(_L1E) {
1167                 *       DBGO("\\_GPE\\_L1E\n")
1168                 * }
1169                 */
1170
1171                 /*  SATA SCI event - Moved to sata.asl */
1172                 /* Method(_L1F) {
1173                 *        DBGO("\\_GPE\\_L1F\n")
1174                 * }
1175                 */
1176
1177         }       /* End Scope GPE */
1178
1179         #include "acpi/usb.asl"
1180
1181         /* System Bus */
1182         Scope(\_SB) { /* Start \_SB scope */
1183                 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1184
1185                 /*  _SB.PCI0 */
1186                 /* Note: Only need HID on Primary Bus */
1187                 Device(PCI0) {
1188                         External (TOM1)
1189                         External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1190                         Name(_HID, EISAID("PNP0A03"))
1191                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1192                         Method(_BBN, 0) { /* Bus number = 0 */
1193                                 Return(0)
1194                         }
1195                         Method(_STA, 0) {
1196                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1197                                 Return(0x0B)     /* Status is visible */
1198                         }
1199
1200                         Method(_PRT,0) {
1201                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1202                                 Return (PR0)                  /* PIC Mode */
1203                         } /* end _PRT */
1204
1205                         /* Describe the Northbridge devices */
1206                         Device(AMRT) {
1207                                 Name(_ADR, 0x00000000)
1208                         } /* end AMRT */
1209
1210                         /* The internal GFX bridge */
1211                         Device(AGPB) {
1212                                 Name(_ADR, 0x00010000)
1213                                 Name(_PRW, Package() {0x18, 4})
1214                                 Method(_PRT,0) {
1215                                         Return (APR1)
1216                                 }
1217                         }  /* end AGPB */
1218
1219                         /* The external GFX bridge */
1220                         Device(PBR2) {
1221                                 Name(_ADR, 0x00020000)
1222                                 Name(_PRW, Package() {0x18, 4})
1223                                 Method(_PRT,0) {
1224                                         If(PMOD){ Return(APS2) }   /* APIC mode */
1225                                         Return (PS2)                  /* PIC Mode */
1226                                 } /* end _PRT */
1227                         } /* end PBR2 */
1228
1229                         /* Dev3 is also an external GFX bridge, not used in Herring */
1230
1231                         Device(PBR4) {
1232                                 Name(_ADR, 0x00040000)
1233                                 Name(_PRW, Package() {0x18, 4})
1234                                 Method(_PRT,0) {
1235                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1236                                         Return (PS4)                  /* PIC Mode */
1237                                 } /* end _PRT */
1238                         } /* end PBR4 */
1239
1240                         Device(PBR5) {
1241                                 Name(_ADR, 0x00050000)
1242                                 Name(_PRW, Package() {0x18, 4})
1243                                 Method(_PRT,0) {
1244                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1245                                         Return (PS5)                  /* PIC Mode */
1246                                 } /* end _PRT */
1247                         } /* end PBR5 */
1248
1249                         Device(PBR6) {
1250                                 Name(_ADR, 0x00060000)
1251                                 Name(_PRW, Package() {0x18, 4})
1252                                 Method(_PRT,0) {
1253                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1254                                         Return (PS6)                  /* PIC Mode */
1255                                 } /* end _PRT */
1256                         } /* end PBR6 */
1257
1258                         /* The onboard EtherNet chip */
1259                         Device(PBR7) {
1260                                 Name(_ADR, 0x00070000)
1261                                 Name(_PRW, Package() {0x18, 4})
1262                                 Method(_PRT,0) {
1263                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1264                                         Return (PS7)                  /* PIC Mode */
1265                                 } /* end _PRT */
1266                         } /* end PBR7 */
1267
1268                         /* GPP */
1269                         Device(PBR9) {
1270                                 Name(_ADR, 0x00090000)
1271                                 Name(_PRW, Package() {0x18, 4})
1272                                 Method(_PRT,0) {
1273                                         If(PMOD){ Return(APS9) }   /* APIC mode */
1274                                         Return (PS9)                  /* PIC Mode */
1275                                 } /* end _PRT */
1276                         } /* end PBR9 */
1277
1278                         Device(PBRa) {
1279                                 Name(_ADR, 0x000A0000)
1280                                 Name(_PRW, Package() {0x18, 4})
1281                                 Method(_PRT,0) {
1282                                         If(PMOD){ Return(APSa) }   /* APIC mode */
1283                                         Return (PSa)                  /* PIC Mode */
1284                                 } /* end _PRT */
1285                         } /* end PBRa */
1286
1287                         Device(PBRb) {
1288                                 Name(_ADR, 0x000b0000)
1289                                 Name(_PRW, Package() {0x18, 4})
1290                                 Method(_PRT,0) {
1291                                         If(PMOD){ Return(APSb) }   /* APIC mode */
1292                                         Return (PSb)                  /* PIC Mode */
1293                                 } /* end _PRT */
1294                         } /* end PBRb */
1295
1296                         Device(PBRc) {
1297                                 Name(_ADR, 0x000c0000)
1298                                 Name(_PRW, Package() {0x18, 4})
1299                                 Method(_PRT,0) {
1300                                         If(PMOD){ Return(APSc) }   /* APIC mode */
1301                                         Return (PSc)                  /* PIC Mode */
1302                                 } /* end _PRT */
1303                         } /* end PBRc */
1304
1305
1306                         /* PCI slot 1, 2, 3 */
1307                         Device(PIBR) {
1308                                 Name(_ADR, 0x00140004)
1309                                 Name(_PRW, Package() {0x18, 4})
1310
1311                                 Method(_PRT, 0) {
1312                                         Return (PCIB)
1313                                 }
1314                         }
1315
1316                         /* Describe the Southbridge devices */
1317                         Device(STCR) {
1318                                 Name(_ADR, 0x00110000)
1319                                 #include "acpi/sata.asl"
1320                         } /* end STCR */
1321
1322                         Device(UOH1) {
1323                                 Name(_ADR, 0x00130000)
1324                                 Name(_PRW, Package() {0x0B, 3})
1325                         } /* end UOH1 */
1326
1327                         Device(UOH2) {
1328                                 Name(_ADR, 0x00130001)
1329                                 Name(_PRW, Package() {0x0B, 3})
1330                         } /* end UOH2 */
1331
1332                         Device(UOH3) {
1333                                 Name(_ADR, 0x00130002)
1334                                 Name(_PRW, Package() {0x0B, 3})
1335                         } /* end UOH3 */
1336
1337                         Device(UOH4) {
1338                                 Name(_ADR, 0x00130003)
1339                                 Name(_PRW, Package() {0x0B, 3})
1340                         } /* end UOH4 */
1341
1342                         Device(UOH5) {
1343                                 Name(_ADR, 0x00130004)
1344                                 Name(_PRW, Package() {0x0B, 3})
1345                         } /* end UOH5 */
1346
1347                         Device(UEH1) {
1348                                 Name(_ADR, 0x00130005)
1349                                 Name(_PRW, Package() {0x0B, 3})
1350                         } /* end UEH1 */
1351
1352                         Device(SBUS) {
1353                                 Name(_ADR, 0x00140000)
1354                         } /* end SBUS */
1355
1356                         /* Primary (and only) IDE channel */
1357                         Device(IDEC) {
1358                                 Name(_ADR, 0x00140001)
1359                                 #include "acpi/ide.asl"
1360                         } /* end IDEC */
1361
1362                         Device(AZHD) {
1363                                 Name(_ADR, 0x00140002)
1364                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1365                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1366                                         offset (0x42),
1367                                         NSDI, 1,
1368                                         NSDO, 1,
1369                                         NSEN, 1,
1370                                         offset (0x44),
1371                                         IPCR, 4,
1372                                         offset (0x54),
1373                                         PWST, 2,
1374                                         , 6,
1375                                         PMEB, 1,
1376                                         , 6,
1377                                         PMST, 1,
1378                                         offset (0x62),
1379                                         MMCR, 1,
1380                                         offset (0x64),
1381                                         MMLA, 32,
1382                                         offset (0x68),
1383                                         MMHA, 32,
1384                                         offset (0x6C),
1385                                         MMDT, 16,
1386                                 }
1387
1388                                 Method(_INI) {
1389                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1390                                                 Store(zero, NSEN)
1391                                                 Store(one, NSDO)
1392                                                 Store(one, NSDI)
1393                                         }
1394                                 }
1395                         } /* end AZHD */
1396
1397                         Device(LIBR) {
1398                                 Name(_ADR, 0x00140003)
1399                                 /* Method(_INI) {
1400                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1401                                 } */ /* End Method(_SB.SBRDG._INI) */
1402
1403                                 /* Real Time Clock Device */
1404                                 Device(RTC0) {
1405                                         Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
1406                                         Name(_CRS, ResourceTemplate() {
1407                                                 IRQNoFlags(){8}
1408                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1409                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1410                                         })
1411                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1412
1413                                 Device(TMR) {   /* Timer */
1414                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1415                                         Name(_CRS, ResourceTemplate() {
1416                                                 IRQNoFlags(){0}
1417                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1418                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1419                                         })
1420                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1421
1422                                 Device(SPKR) {  /* Speaker */
1423                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1424                                         Name(_CRS, ResourceTemplate() {
1425                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1426                                         })
1427                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1428
1429                                 Device(PIC) {
1430                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1431                                         Name(_CRS, ResourceTemplate() {
1432                                                 IRQNoFlags(){2}
1433                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1434                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1435                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1436                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1437                                         })
1438                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1439
1440                                 Device(MAD) { /* 8257 DMA */
1441                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1442                                         Name(_CRS, ResourceTemplate() {
1443                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1444                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1445                                                 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1446                                                 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1447                                                 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1448                                                 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1449                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1450                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1451                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1452
1453                                 Device(COPR) {
1454                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1455                                         Name(_CRS, ResourceTemplate() {
1456                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1457                                                 IRQNoFlags(){13}
1458                                         })
1459                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1460
1461                                 Device(HPTM) {
1462                                         Name(_HID,EISAID("PNP0103"))
1463                                         Name(CRS,ResourceTemplate()     {
1464                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1465                                         })
1466                                         Method(_STA, 0) {
1467                                                 Return(0x0F) /* sata is visible */
1468                                         }
1469                                         Method(_CRS, 0) {
1470                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1471                                                 Store(HPBA, HPBA)
1472                                                 Return(CRS)
1473                                         }
1474                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1475                         } /* end LIBR */
1476
1477                         Device(HPBR) {
1478                                 Name(_ADR, 0x00140004)
1479                         } /* end HostPciBr */
1480
1481                         Device(ACAD) {
1482                                 Name(_ADR, 0x00140005)
1483                         } /* end Ac97audio */
1484
1485                         Device(ACMD) {
1486                                 Name(_ADR, 0x00140006)
1487                         } /* end Ac97modem */
1488
1489                         /* ITE8718 Support */
1490                         OperationRegion (IOID, SystemIO, 0x2E, 0x02)    /* sometimes it is 0x4E */
1491                                 Field (IOID, ByteAcc, NoLock, Preserve)
1492                                 {
1493                                         SIOI,   8,    SIOD,   8         /* 0x2E and 0x2F */
1494                                 }
1495
1496                         IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1497                         {
1498                                         Offset (0x07),
1499                                 LDN,    8,      /* Logical Device Number */
1500                                         Offset (0x20),
1501                                 CID1,   8,      /* Chip ID Byte 1, 0x87 */
1502                                 CID2,   8,      /* Chip ID Byte 2, 0x12 */
1503                                         Offset (0x30),
1504                                 ACTR,   8,      /* Function activate */
1505                                         Offset (0xF0),
1506                                 APC0,   8,      /* APC/PME Event Enable Register */
1507                                 APC1,   8,      /* APC/PME Status Register */
1508                                 APC2,   8,      /* APC/PME Control Register 1 */
1509                                 APC3,   8,      /* Environment Controller Special Configuration Register */
1510                                 APC4,   8       /* APC/PME Control Register 2 */
1511                         }
1512
1513                         /* Enter the 8718 MB PnP Mode */
1514                         Method (EPNP)
1515                         {
1516                                 Store(0x87, SIOI)
1517                                 Store(0x01, SIOI)
1518                                 Store(0x55, SIOI)
1519                                 Store(0x55, SIOI) /* 8718 magic number */
1520                         }
1521                         /* Exit the 8718 MB PnP Mode */
1522                         Method (XPNP)
1523                         {
1524                                 Store (0x02, SIOI)
1525                                 Store (0x02, SIOD)
1526                         }
1527                         /*
1528                          * Keyboard PME is routed to SB700 Gevent3. We can wake
1529                          * up the system by pressing the key.
1530                          */
1531                         Method (SIOS, 1)
1532                         {
1533                                 /* We only enable KBD PME for S5. */
1534                                 If (LLess (Arg0, 0x05))
1535                                 {
1536                                         EPNP()
1537                                         /* DBGO("8718F\n") */
1538
1539                                         Store (0x4, LDN)
1540                                         Store (One, ACTR)  /* Enable EC */
1541                                         /*
1542                                         Store (0x4, LDN)
1543                                         Store (0x04, APC4)
1544                                         */  /* falling edge. which mode? Not sure. */
1545
1546                                         Store (0x4, LDN)
1547                                         Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1548                                         Store (0x4, LDN)
1549                                         Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1550
1551                                         XPNP()
1552                                 }
1553                         }
1554                         Method (SIOW, 1)
1555                         {
1556                                 EPNP()
1557                                 Store (0x4, LDN)
1558                                 Store (Zero, APC0) /* disable keyboard PME */
1559                                 Store (0x4, LDN)
1560                                 Store (0xFF, APC1) /* clear keyboard PME status */
1561                                 XPNP()
1562                         }
1563
1564                         Name(CRES, ResourceTemplate() {
1565                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1566
1567                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1568                                         0x0000,                 /* address granularity */
1569                                         0x0000,                 /* range minimum */
1570                                         0x0CF7,                 /* range maximum */
1571                                         0x0000,                 /* translation */
1572                                         0x0CF8                  /* length */
1573                                 )
1574
1575                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1576                                         0x0000,                 /* address granularity */
1577                                         0x0D00,                 /* range minimum */
1578                                         0xFFFF,                 /* range maximum */
1579                                         0x0000,                 /* translation */
1580                                         0xF300                  /* length */
1581                                 )
1582
1583 #if 0
1584                                 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1585                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1586                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1587                                 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
1588
1589                                 /* DRAM Memory from 1MB to TopMem */
1590                                 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)   /* 1MB to TopMem */
1591
1592                                 /* BIOS space just below 4GB */
1593                                 DWORDMemory(
1594                                         ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1595                                         0x00,                   /* Granularity */
1596                                         0x00000000,             /* Min */
1597                                         0x00000000,             /* Max */
1598                                         0x00000000,             /* Translation */
1599                                         0x00000001,             /* Max-Min, RLEN */
1600                                         ,,
1601                                         PCBM
1602                                 )
1603
1604                                 /* DRAM memory from 4GB to TopMem2 */
1605                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1606                                         0x00000000,             /* Granularity */
1607                                         0x00000000,             /* Min */
1608                                         0x00000000,             /* Max */
1609                                         0x00000000,             /* Translation */
1610                                         0x00000001,             /* Max-Min, RLEN */
1611                                         ,,
1612                                         DMHI
1613                                 )
1614
1615                                 /* BIOS space just below 16EB */
1616                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1617                                         0x00000000,             /* Granularity */
1618                                         0x00000000,             /* Min */
1619                                         0x00000000,             /* Max */
1620                                         0x00000000,             /* Translation */
1621                                         0x00000001,             /* Max-Min, RLEN */
1622                                         ,,
1623                                         PEBM
1624                                 )
1625 #endif
1626
1627                                 /* memory space for PCI BARs below 4GB */
1628                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1629                         }) /* End Name(_SB.PCI0.CRES) */
1630
1631                         Method(_CRS, 0) {
1632                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1633
1634 #if 0
1635                                 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1636                                 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1637                                 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1638                                 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1639                                 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1640                                 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1641
1642                                 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1643                                 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1644                                 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1645                                 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1646
1647                                 If(LGreater(LOMH, 0xC0000)){
1648                                         Store(0xC0000, EM1B)    /* Hole above C0000 and below E0000 */
1649                                         Subtract(LOMH, 0xC0000, EM1L)   /* subtract start, assumes allocation from C0000 going up */
1650                                 }
1651
1652                                 /* Set size of memory from 1MB to TopMem */
1653                                 Subtract(TOM1, 0x100000, DMLL)
1654
1655                                 /*
1656                                 * If(LNotEqual(TOM2, 0x00000000)){
1657                                 *       Store(0x100000000,DMHB)                 DRAM from 4GB to TopMem2
1658                                 *       Subtract(TOM2, 0x100000000, DMHL)
1659                                 * }
1660                                 */
1661
1662                                 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1663                                 If(LEqual(TOM2, 0x00000000)){
1664                                         Store(PBAD,PBMB)                        /* Reserve the "BIOS" space */
1665                                         Store(PBLN,PBML)
1666                                 }
1667                                 Else {  /* Otherwise, put the BIOS just below 16EB */
1668                                         ShiftLeft(PBAD,16,EBMB)         /* Reserve the "BIOS" space */
1669                                         Store(PBLN,EBML)
1670                                 }
1671 #endif
1672
1673                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1674                                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1675                                 /*
1676                                  * Declare memory between TOM1 and 4GB as available
1677                                  * for PCI MMIO.
1678                                  * Use ShiftLeft to avoid 64bit constant (for XP).
1679                                  * This will work even if the OS does 32bit arithmetic, as
1680                                  * 32bit (0x00000000 - TOM1) will wrap and give the same
1681                                  * result as 64bit (0x100000000 - TOM1).
1682                                  */
1683                                 Store(TOM1, MM1B)
1684                                 ShiftLeft(0x10000000, 4, Local0)
1685                                 Subtract(Local0, TOM1, Local0)
1686                                 Store(Local0, MM1L)
1687
1688                                 Return(CRES) /* note to change the Name buffer */
1689                         }  /* end of Method(_SB.PCI0._CRS) */
1690
1691                         /*
1692                         *
1693                         *               FIRST METHOD CALLED UPON BOOT
1694                         *
1695                         *  1. If debugging, print current OS and ACPI interpreter.
1696                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1697                         *     value is based on user choice in BIOS setup.
1698                         */
1699                         Method(_INI, 0) {
1700                                 /* DBGO("\\_SB\\_INI\n") */
1701                                 /* DBGO("   DSDT.ASL code from ") */
1702                                 /* DBGO(__DATE__) */
1703                                 /* DBGO(" ") */
1704                                 /* DBGO(__TIME__) */
1705                                 /* DBGO("\n   Sleep states supported: ") */
1706                                 /* DBGO("\n") */
1707                                 /* DBGO("   \\_OS=") */
1708                                 /* DBGO(\_OS) */
1709                                 /* DBGO("\n   \\_REV=") */
1710                                 /* DBGO(\_REV) */
1711                                 /* DBGO("\n") */
1712
1713                                 /* Determine the OS we're running on */
1714                                 CkOT()
1715
1716                                 /* On older chips, clear PciExpWakeDisEn */
1717                                 /*if (LLessEqual(\SBRI, 0x13)) {
1718                                 *       Store(0,\PWDE)
1719                                 * }
1720                                 */
1721                         } /* End Method(_SB._INI) */
1722                 } /* End Device(PCI0)  */
1723
1724                 Device(PWRB) {  /* Start Power button device */
1725                         Name(_HID, EISAID("PNP0C0C"))
1726                         Name(_UID, 0xAA)
1727                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1728                         Name(_STA, 0x0B) /* sata is invisible */
1729                 }
1730         } /* End \_SB scope */
1731
1732         Scope(\_SI) {
1733                 Method(_SST, 1) {
1734                         /* DBGO("\\_SI\\_SST\n") */
1735                         /* DBGO("   New Indicator state: ") */
1736                         /* DBGO(Arg0) */
1737                         /* DBGO("\n") */
1738                 }
1739         } /* End Scope SI */
1740
1741         /* SMBUS Support */
1742         Mutex (SBX0, 0x00)
1743         OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1744                 Field (SMB0, ByteAcc, NoLock, Preserve) {
1745                         HSTS,   8, /* SMBUS status */
1746                         SSTS,   8,  /* SMBUS slave status */
1747                         HCNT,   8,  /* SMBUS control */
1748                         HCMD,   8,  /* SMBUS host cmd */
1749                         HADD,   8,  /* SMBUS address */
1750                         DAT0,   8,  /* SMBUS data0 */
1751                         DAT1,   8,  /* SMBUS data1 */
1752                         BLKD,   8,  /* SMBUS block data */
1753                         SCNT,   8,  /* SMBUS slave control */
1754                         SCMD,   8,  /* SMBUS shaow cmd */
1755                         SEVT,   8,  /* SMBUS slave event */
1756                         SDAT,   8  /* SMBUS slave data */
1757         }
1758
1759         Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1760                 Store (0x1E, HSTS)
1761                 Store (0xFA, Local0)
1762                 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1763                         Stall (0x64)
1764                         Decrement (Local0)
1765                 }
1766
1767                 Return (Local0)
1768         }
1769
1770         Method (SWTC, 1, NotSerialized) {
1771                 Store (Arg0, Local0)
1772                 Store (0x07, Local2)
1773                 Store (One, Local1)
1774                 While (LEqual (Local1, One)) {
1775                         Store (And (HSTS, 0x1E), Local3)
1776                         If (LNotEqual (Local3, Zero)) { /* read sucess */
1777                                 If (LEqual (Local3, 0x02)) {
1778                                         Store (Zero, Local2)
1779                                 }
1780
1781                                 Store (Zero, Local1)
1782                         }
1783                         Else {
1784                                 If (LLess (Local0, 0x0A)) { /* read failure */
1785                                         Store (0x10, Local2)
1786                                         Store (Zero, Local1)
1787                                 }
1788                                 Else {
1789                                         Sleep (0x0A) /* 10 ms, try again */
1790                                         Subtract (Local0, 0x0A, Local0)
1791                                 }
1792                         }
1793                 }
1794
1795                 Return (Local2)
1796         }
1797
1798         Method (SMBR, 3, NotSerialized) {
1799                 Store (0x07, Local0)
1800                 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1801                         Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1802                         If (LEqual (Local0, Zero)) {
1803                                 Release (SBX0)
1804                                 Return (0x0)
1805                         }
1806
1807                         Store (0x1F, HSTS)
1808                         Store (Or (ShiftLeft (Arg1, One), One), HADD)
1809                         Store (Arg2, HCMD)
1810                         If (LEqual (Arg0, 0x07)) {
1811                                 Store (0x48, HCNT) /* read byte */
1812                         }
1813
1814                         Store (SWTC (0x03E8), Local1) /* 1000 ms */
1815                         If (LEqual (Local1, Zero)) {
1816                                 If (LEqual (Arg0, 0x07)) {
1817                                         Store (DAT0, Local0)
1818                                 }
1819                         }
1820                         Else {
1821                                 Store (Local1, Local0)
1822                         }
1823
1824                         Release (SBX0)
1825                 }
1826
1827                 /* DBGO("the value of SMBusData0 register ") */
1828                 /* DBGO(Arg2) */
1829                 /* DBGO(" is ") */
1830                 /* DBGO(Local0) */
1831                 /* DBGO("\n") */
1832
1833                 Return (Local0)
1834         }
1835
1836         /* THERMAL */
1837         Scope(\_TZ) {
1838                 Name (KELV, 2732)
1839                 Name (THOT, 800)
1840                 Name (TCRT, 850)
1841
1842                 ThermalZone(TZ00) {
1843                         Method(_AC0,0) {        /* Active Cooling 0 (0=highest fan speed) */
1844                                 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1845                                 Return(Add(0, 2730))
1846                         }
1847                         Method(_AL0,0) {        /* Returns package of cooling device to turn on */
1848                                 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1849                                 Return(Package() {\_TZ.TZ00.FAN0})
1850                         }
1851                         Device (FAN0) {
1852                                 Name(_HID, EISAID("PNP0C0B"))
1853                                 Name(_PR0, Package() {PFN0})
1854                         }
1855
1856                         PowerResource(PFN0,0,0) {
1857                                 Method(_STA) {
1858                                         Store(0xF,Local0)
1859                                         Return(Local0)
1860                                 }
1861                                 Method(_ON) {
1862                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1863                                 }
1864                                 Method(_OFF) {
1865                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1866                                 }
1867                         }
1868
1869                         Method(_HOT,0) {        /* return hot temp in tenths degree Kelvin */
1870                                 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1871                                 Return (Add (THOT, KELV))
1872                         }
1873                         Method(_CRT,0) {        /* return critical temp in tenths degree Kelvin */
1874                                 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1875                                 Return (Add (TCRT, KELV))
1876                         }
1877                         Method(_TMP,0) {        /* return current temp of this zone */
1878                                 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1879                                 If (LGreater (Local0, 0x10)) {
1880                                         Store (Local0, Local1)
1881                                 }
1882                                 Else {
1883                                         Add (Local0, THOT, Local0)
1884                                         Return (Add (400, KELV))
1885                                 }
1886
1887                                 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1888                                 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1889                                 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1890                                 If (LGreater (Local0, 0x10)) {
1891                                         If (LGreater (Local0, Local1)) {
1892                                                 Store (Local0, Local1)
1893                                         }
1894
1895                                         Multiply (Local1, 10, Local1)
1896                                         Return (Add (Local1, KELV))
1897                                 }
1898                                 Else {
1899                                         Add (Local0, THOT, Local0)
1900                                         Return (Add (400 , KELV))
1901                                 }
1902                         } /* end of _TMP */
1903                 } /* end of TZ00 */
1904         }
1905 }
1906 /* End of ASL file */