2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
24 #include "routing.asl"
28 /* Routing is in System Bus scope */
32 /* Bus 0, Dev 0 - RS780 Host Controller */
33 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
34 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
35 Package(){0x0002FFFF, 0, INTC, 0 },
36 Package(){0x0002FFFF, 1, INTD, 0 },
37 Package(){0x0002FFFF, 2, INTA, 0 },
38 Package(){0x0002FFFF, 3, INTB, 0 },
39 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
40 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
41 Package(){0x0004FFFF, 0, INTA, 0 },
42 Package(){0x0004FFFF, 1, INTB, 0 },
43 Package(){0x0004FFFF, 2, INTC, 0 },
44 Package(){0x0004FFFF, 3, INTD, 0 },
45 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
46 /* Package(){0x0005FFFF, 0, INTB, 0 }, */
47 /* Package(){0x0005FFFF, 1, INTC, 0 }, */
48 /* Package(){0x0005FFFF, 2, INTD, 0 }, */
49 /* Package(){0x0005FFFF, 3, INTA, 0 }, */
50 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
51 Package(){0x0006FFFF, 0, INTC, 0 },
52 Package(){0x0006FFFF, 1, INTD, 0 },
53 Package(){0x0006FFFF, 2, INTA, 0 },
54 Package(){0x0006FFFF, 3, INTB, 0 },
55 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
56 Package(){0x0007FFFF, 0, INTD, 0 },
57 Package(){0x0007FFFF, 1, INTA, 0 },
58 Package(){0x0007FFFF, 2, INTB, 0 },
59 Package(){0x0007FFFF, 3, INTC, 0 },
60 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
63 /* Bus 0, Dev 17 - SATA controller #2 */
64 /* Bus 0, Dev 18 - SATA controller #1 */
65 Package(){0x0011FFFF, 1, INTA, 0 },
67 /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
68 Package(){0x0012FFFF, 0, INTA, 0 },
69 Package(){0x0012FFFF, 1, INTB, 0 },
70 Package(){0x0013FFFF, 0, INTA, 0 },
71 Package(){0x0013FFFF, 1, INTB, 0 },
72 Package(){0x0014FFFF, 2, INTA, 0 },
74 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
75 Package(){0x0014FFFF, 0, INTA, 0 },
76 Package(){0x0014FFFF, 1, INTB, 0 },
77 Package(){0x0014FFFF, 2, INTC, 0 },
78 Package(){0x0014FFFF, 3, INTD, 0 },
82 /* NB devices in APIC mode */
83 /* Bus 0, Dev 0 - RS780 Host Controller */
85 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
86 /* Package(){0x0001FFFF, 0, 0, 18 }, */
87 /* package(){0x0001FFFF, 1, 0, 19 }, */
89 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
90 Package(){0x0002FFFF, 0, 0, 18 },
91 /* Package(){0x0002FFFF, 1, 0, 19 }, */
92 /* Package(){0x0002FFFF, 2, 0, 16 }, */
93 /* Package(){0x0002FFFF, 3, 0, 17 }, */
95 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
96 Package(){0x0003FFFF, 0, 0, 19 },
98 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
99 Package(){0x0004FFFF, 0, 0, 16 },
100 /* Package(){0x0004FFFF, 1, 0, 17 }, */
101 /* Package(){0x0004FFFF, 2, 0, 18 }, */
102 /* Package(){0x0004FFFF, 3, 0, 19 }, */
104 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
105 /* Package(){0x0005FFFF, 0, 0, 17 }, */
106 /* Package(){0x0005FFFF, 1, 0, 18 }, */
107 /* Package(){0x0005FFFF, 2, 0, 19 }, */
108 /* Package(){0x0005FFFF, 3, 0, 16 }, */
110 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
111 /* Package(){0x0006FFFF, 0, 0, 18 }, */
112 /* Package(){0x0006FFFF, 1, 0, 19 }, */
113 /* Package(){0x0006FFFF, 2, 0, 16 }, */
114 /* Package(){0x0006FFFF, 3, 0, 17 }, */
116 /* Bus 0, Dev 7 - PCIe Bridge for network card */
117 /* Package(){0x0007FFFF, 0, 0, 19 }, */
118 /* Package(){0x0007FFFF, 1, 0, 16 }, */
119 /* Package(){0x0007FFFF, 2, 0, 17 }, */
120 /* Package(){0x0007FFFF, 3, 0, 18 }, */
122 /* Bus 0, Dev 9 - PCIe Bridge for network card */
123 Package(){0x0009FFFF, 0, 0, 17 },
124 /* Package(){0x0009FFFF, 1, 0, 16 }, */
125 /* Package(){0x0009FFFF, 2, 0, 17 }, */
126 /* Package(){0x0009FFFF, 3, 0, 18 }, */
127 /* Bus 0, Dev A - PCIe Bridge for network card */
128 Package(){0x000AFFFF, 0, 0, 18 },
129 /* Package(){0x000AFFFF, 1, 0, 16 }, */
130 /* Package(){0x000AFFFF, 2, 0, 17 }, */
131 /* Package(){0x000AFFFF, 3, 0, 18 }, */
132 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
134 /* SB devices in APIC mode */
135 /* Bus 0, Dev 17 - SATA controller #2 */
136 /* Bus 0, Dev 18 - SATA controller #1 */
137 Package(){0x0011FFFF, 0, 0, 22 },
139 /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
140 Package(){0x0012FFFF, 0, 0, 16 },
141 Package(){0x0012FFFF, 1, 0, 17 },
142 Package(){0x0013FFFF, 0, 0, 18 },
143 Package(){0x0013FFFF, 1, 0, 19 },
144 Package(){0x0014FFFF, 0, 0, 16 },
145 /* Package(){0x00130004, 2, 0, 18 }, */
146 /* Package(){0x00130005, 3, 0, 19 }, */
148 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
149 Package(){0x0014FFFF, 0, 0, 16 },
150 Package(){0x0014FFFF, 1, 0, 17 },
151 Package(){0x0014FFFF, 2, 0, 18 },
152 Package(){0x0014FFFF, 3, 0, 19 },
153 /* Package(){0x00140004, 2, 0, 18 }, */
154 /* Package(){0x00140004, 3, 0, 19 }, */
155 /* Package(){0x00140005, 1, 0, 17 }, */
156 /* Package(){0x00140006, 1, 0, 17 }, */
160 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
161 Package(){0x0005FFFF, 0, INTA, 0 },
162 Package(){0x0005FFFF, 1, INTB, 0 },
163 Package(){0x0005FFFF, 2, INTC, 0 },
164 Package(){0x0005FFFF, 3, INTD, 0 },
167 Name(APR1, Package(){
168 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
169 Package(){0x0005FFFF, 0, 0, 18 },
170 Package(){0x0005FFFF, 1, 0, 19 },
171 /* Package(){0x0005FFFF, 2, 0, 20 }, */
172 /* Package(){0x0005FFFF, 3, 0, 17 }, */
176 /* The external GFX - Hooked to PCIe slot 2 */
177 Package(){0x0000FFFF, 0, INTC, 0 },
178 Package(){0x0000FFFF, 1, INTD, 0 },
179 Package(){0x0000FFFF, 2, INTA, 0 },
180 Package(){0x0000FFFF, 3, INTB, 0 },
183 Name(APS2, Package(){
184 /* The external GFX - Hooked to PCIe slot 2 */
185 Package(){0x0000FFFF, 0, 0, 18 },
186 Package(){0x0000FFFF, 1, 0, 19 },
187 Package(){0x0000FFFF, 2, 0, 16 },
188 Package(){0x0000FFFF, 3, 0, 17 },
192 /* PCIe slot - Hooked to PCIe slot 4 */
193 Package(){0x0000FFFF, 0, INTA, 0 },
194 Package(){0x0000FFFF, 1, INTB, 0 },
195 Package(){0x0000FFFF, 2, INTC, 0 },
196 Package(){0x0000FFFF, 3, INTD, 0 },
199 Name(APS4, Package(){
200 /* PCIe slot - Hooked to PCIe slot 4 */
201 Package(){0x0000FFFF, 0, 0, 16 },
202 Package(){0x0000FFFF, 1, 0, 17 },
203 Package(){0x0000FFFF, 2, 0, 18 },
204 Package(){0x0000FFFF, 3, 0, 19 },
208 /* PCIe slot - Hooked to PCIe slot 5 */
209 Package(){0x0000FFFF, 0, INTB, 0 },
210 Package(){0x0000FFFF, 1, INTC, 0 },
211 Package(){0x0000FFFF, 2, INTD, 0 },
212 Package(){0x0000FFFF, 3, INTA, 0 },
215 Name(APS5, Package(){
216 /* PCIe slot - Hooked to PCIe slot 5 */
217 Package(){0x0000FFFF, 0, 0, 17 },
218 Package(){0x0000FFFF, 1, 0, 18 },
219 Package(){0x0000FFFF, 2, 0, 19 },
220 Package(){0x0000FFFF, 3, 0, 16 },
224 /* PCIe slot - Hooked to PCIe slot 6 */
225 Package(){0x0000FFFF, 0, INTC, 0 },
226 Package(){0x0000FFFF, 1, INTD, 0 },
227 Package(){0x0000FFFF, 2, INTA, 0 },
228 Package(){0x0000FFFF, 3, INTB, 0 },
231 Name(APS6, Package(){
232 /* PCIe slot - Hooked to PCIe slot 6 */
233 Package(){0x0000FFFF, 0, 0, 18 },
234 Package(){0x0000FFFF, 1, 0, 19 },
235 Package(){0x0000FFFF, 2, 0, 16 },
236 Package(){0x0000FFFF, 3, 0, 17 },
240 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
241 Package(){0x0000FFFF, 0, INTD, 0 },
242 Package(){0x0000FFFF, 1, INTA, 0 },
243 Package(){0x0000FFFF, 2, INTB, 0 },
244 Package(){0x0000FFFF, 3, INTC, 0 },
247 Name(APS7, Package(){
248 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
249 Package(){0x0000FFFF, 0, 0, 19 },
250 Package(){0x0000FFFF, 1, 0, 16 },
251 Package(){0x0000FFFF, 2, 0, 17 },
252 Package(){0x0000FFFF, 3, 0, 18 },
255 /* PCIe slot - Hooked to PCIe slot 9 */
256 Package(){0x0000FFFF, 0, INTD, 0 },
257 Package(){0x0000FFFF, 1, INTA, 0 },
258 Package(){0x0000FFFF, 2, INTB, 0 },
259 Package(){0x0000FFFF, 3, INTC, 0 },
262 Name(APS9, Package(){
263 /* PCIe slot - Hooked to PCIe slot 9 */
264 Package(){0x0000FFFF, 0, 0, 17 },
265 Package(){0x0000FFFF, 1, 0, 18 },
266 Package(){0x0000FFFF, 2, 0, 19 },
267 Package(){0x0000FFFF, 3, 0, 16 },
270 /* PCIe slot - Hooked to PCIe slot 10 */
271 Package(){0x0000FFFF, 0, INTD, 0 },
272 Package(){0x0000FFFF, 1, INTA, 0 },
273 Package(){0x0000FFFF, 2, INTB, 0 },
274 Package(){0x0000FFFF, 3, INTC, 0 },
277 Name(APSa, Package(){
278 /* PCIe slot - Hooked to PCIe slot 10 */
279 Package(){0x0000FFFF, 0, 0, 18 },
280 Package(){0x0000FFFF, 1, 0, 19 },
281 Package(){0x0000FFFF, 2, 0, 16 },
282 Package(){0x0000FFFF, 3, 0, 17 },
285 Name(PCIB, Package(){
286 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
287 Package(){0x0005FFFF, 0, 0, 0x14 },
288 Package(){0x0005FFFF, 1, 0, 0x15 },
289 Package(){0x0005FFFF, 2, 0, 0x16 },
290 Package(){0x0005FFFF, 3, 0, 0x17 },
291 Package(){0x0006FFFF, 0, 0, 0x15 },
292 Package(){0x0006FFFF, 1, 0, 0x16 },
293 Package(){0x0006FFFF, 2, 0, 0x17 },
294 Package(){0x0006FFFF, 3, 0, 0x14 },
295 Package(){0x0007FFFF, 0, 0, 0x16 },
296 Package(){0x0007FFFF, 1, 0, 0x17 },
297 Package(){0x0007FFFF, 2, 0, 0x14 },
298 Package(){0x0007FFFF, 3, 0, 0x15 },