src/mainboard/asus/m4a785-m/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",           /* Output filename */
  23         "DSDT",                 /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "AMD   ",               /* OEMID */
  26         "TILAPIA ",          /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include "../../../arch/x86/acpi/debug.asl" */               /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, 0xE0000000)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* USB overcurrent mapping pins.   */
  45         Name(UOM0, 0)
  46         Name(UOM1, 2)
  47         Name(UOM2, 0)
  48         Name(UOM3, 7)
  49         Name(UOM4, 2)
  50         Name(UOM5, 2)
  51         Name(UOM6, 6)
  52         Name(UOM7, 2)
  53         Name(UOM8, 6)
  54         Name(UOM9, 6)
  55
  56         /* Some global data */
  57         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
  58         Name(OSV, Ones) /* Assume nothing */
  59         Name(PMOD, One) /* Assume APIC */
  60
  61         /*
  62          * Processor Object
  63          *
  64          */
  65         Scope (\_PR) {          /* define processor scope */
  66                 Processor(
  67                         CPU0,           /* name space name */
  68                         0,              /* Unique number for this processor */
  69                         0x808,          /* PBLK system I/O address !hardcoded! */
  70                         0x06            /* PBLKLEN for boot processor */
  71                         ) {
  72                         #include "acpi/cpstate.asl"
  73                 }
  74
  75                 Processor(
  76                         CPU1,           /* name space name */
  77                         1,              /* Unique number for this processor */
  78                         0x0000,         /* PBLK system I/O address !hardcoded! */
  79                         0x00            /* PBLKLEN for boot processor */
  80                         ) {
  81                         #include "acpi/cpstate.asl"
  82                 }
  83
  84                 Processor(
  85                         CPU2,           /* name space name */
  86                         2,              /* Unique number for this processor */
  87                         0x0000,         /* PBLK system I/O address !hardcoded! */
  88                         0x00            /* PBLKLEN for boot processor */
  89                         ) {
  90                         #include "acpi/cpstate.asl"
  91                 }
  92
  93                 Processor(
  94                         CPU3,           /* name space name */
  95                         3,              /* Unique number for this processor */
  96                         0x0000,         /* PBLK system I/O address !hardcoded! */
  97                         0x00            /* PBLKLEN for boot processor */
  98                         ) {
  99                         #include "acpi/cpstate.asl"
 100                 }
 101         } /* End _PR scope */
 102
 103         /* PIC IRQ mapping registers, C00h-C01h */
 104         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 105                 Field(PRQM, ByteAcc, NoLock, Preserve) {
 106                 PRQI, 0x00000008,
 107                 PRQD, 0x00000008,  /* Offset: 1h */
 108         }
 109         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 110                 PINA, 0x00000008,       /* Index 0  */
 111                 PINB, 0x00000008,       /* Index 1 */
 112                 PINC, 0x00000008,       /* Index 2 */
 113                 PIND, 0x00000008,       /* Index 3 */
 114                 AINT, 0x00000008,       /* Index 4 */
 115                 SINT, 0x00000008,       /*  Index 5 */
 116                 , 0x00000008,                /* Index 6 */
 117                 AAUD, 0x00000008,       /* Index 7 */
 118                 AMOD, 0x00000008,       /* Index 8 */
 119                 PINE, 0x00000008,       /* Index 9 */
 120                 PINF, 0x00000008,       /* Index A */
 121                 PING, 0x00000008,       /* Index B */
 122                 PINH, 0x00000008,       /* Index C */
 123         }
 124
 125         /* PCI Error control register */
 126         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 127                 Field(PERC, ByteAcc, NoLock, Preserve) {
 128                 SENS, 0x00000001,
 129                 PENS, 0x00000001,
 130                 SENE, 0x00000001,
 131                 PENE, 0x00000001,
 132         }
 133
 134         /* Client Management index/data registers */
 135         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 136                 Field(CMT, ByteAcc, NoLock, Preserve) {
 137                 CMTI,      8,
 138                 /* Client Management Data register */
 139                 G64E,   1,
 140                 G64O,      1,
 141                 G32O,      2,
 142                 ,       2,
 143                 GPSL,     2,
 144         }
 145
 146         /* GPM Port register */
 147         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 148                 Field(GPT, ByteAcc, NoLock, Preserve) {
 149                 GPB0,1,
 150                 GPB1,1,
 151                 GPB2,1,
 152                 GPB3,1,
 153                 GPB4,1,
 154                 GPB5,1,
 155                 GPB6,1,
 156                 GPB7,1,
 157         }
 158
 159         /* Flash ROM program enable register */
 160         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 161                 Field(FRE, ByteAcc, NoLock, Preserve) {
 162                 ,     0x00000006,
 163                 FLRE, 0x00000001,
 164         }
 165
 166         /* PM2 index/data registers */
 167         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 168                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 169                 PM2I, 0x00000008,
 170                 PM2D, 0x00000008,
 171         }
 172
 173         /* Power Management I/O registers */
 174         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 175                 Field(PIOR, ByteAcc, NoLock, Preserve) {
 176                 PIOI, 0x00000008,
 177                 PIOD, 0x00000008,
 178         }
 179         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 180                 Offset(0x00),   /* MiscControl */
 181                 , 1,
 182                 T1EE, 1,
 183                 T2EE, 1,
 184                 Offset(0x01),   /* MiscStatus */
 185                 , 1,
 186                 T1E, 1,
 187                 T2E, 1,
 188                 Offset(0x04),   /* SmiWakeUpEventEnable3 */
 189                 , 7,
 190                 SSEN, 1,
 191                 Offset(0x07),   /* SmiWakeUpEventStatus3 */
 192                 , 7,
 193                 CSSM, 1,
 194                 Offset(0x10),   /* AcpiEnable */
 195                 , 6,
 196                 PWDE, 1,
 197                 Offset(0x1C),   /* ProgramIoEnable */
 198                 , 3,
 199                 MKME, 1,
 200                 IO3E, 1,
 201                 IO2E, 1,
 202                 IO1E, 1,
 203                 IO0E, 1,
 204                 Offset(0x1D),   /* IOMonitorStatus */
 205                 , 3,
 206                 MKMS, 1,
 207                 IO3S, 1,
 208                 IO2S, 1,
 209                 IO1S, 1,
 210                 IO0S,1,
 211                 Offset(0x20),   /* AcpiPmEvtBlk */
 212                 APEB, 16,
 213                 Offset(0x36),   /* GEvtLevelConfig */
 214                 , 6,
 215                 ELC6, 1,
 216                 ELC7, 1,
 217                 Offset(0x37),   /* GPMLevelConfig0 */
 218                 , 3,
 219                 PLC0, 1,
 220                 PLC1, 1,
 221                 PLC2, 1,
 222                 PLC3, 1,
 223                 PLC8, 1,
 224                 Offset(0x38),   /* GPMLevelConfig1 */
 225                 , 1,
 226                  PLC4, 1,
 227                  PLC5, 1,
 228                 , 1,
 229                  PLC6, 1,
 230                  PLC7, 1,
 231                 Offset(0x3B),   /* PMEStatus1 */
 232                 GP0S, 1,
 233                 GM4S, 1,
 234                 GM5S, 1,
 235                 APS, 1,
 236                 GM6S, 1,
 237                 GM7S, 1,
 238                 GP2S, 1,
 239                 STSS, 1,
 240                 Offset(0x55),   /* SoftPciRst */
 241                 SPRE, 1,
 242                 , 1,
 243                 , 1,
 244                 PNAT, 1,
 245                 PWMK, 1,
 246                 PWNS, 1,
 247
 248                 /*      Offset(0x61), */        /*  Options_1 */
 249                 /*              ,7,  */
 250                 /*              R617,1, */
 251
 252                 Offset(0x65),   /* UsbPMControl */
 253                 , 4,
 254                 URRE, 1,
 255                 Offset(0x68),   /* MiscEnable68 */
 256                 , 3,
 257                 TMTE, 1,
 258                 , 1,
 259                 Offset(0x92),   /* GEVENTIN */
 260                 , 7,
 261                 E7IS, 1,
 262                 Offset(0x96),   /* GPM98IN */
 263                 G8IS, 1,
 264                 G9IS, 1,
 265                 Offset(0x9A),   /* EnhanceControl */
 266                 ,7,
 267                 HPDE, 1,
 268                 Offset(0xA8),   /* PIO7654Enable */
 269                 IO4E, 1,
 270                 IO5E, 1,
 271                 IO6E, 1,
 272                 IO7E, 1,
 273                 Offset(0xA9),   /* PIO7654Status */
 274                 IO4S, 1,
 275                 IO5S, 1,
 276                 IO6S, 1,
 277                 IO7S, 1,
 278         }
 279
 280         /* PM1 Event Block
 281         * First word is PM1_Status, Second word is PM1_Enable
 282         */
 283         OperationRegion(P1EB, SystemIO, APEB, 0x04)
 284                 Field(P1EB, ByteAcc, NoLock, Preserve) {
 285                 TMST, 1,
 286                 ,    3,
 287                 BMST,    1,
 288                 GBST,   1,
 289                 Offset(0x01),
 290                 PBST, 1,
 291                 , 1,
 292                 RTST, 1,
 293                 , 3,
 294                 PWST, 1,
 295                 SPWS, 1,
 296                 Offset(0x02),
 297                 TMEN, 1,
 298                 , 4,
 299                 GBEN, 1,
 300                 Offset(0x03),
 301                 PBEN, 1,
 302                 , 1,
 303                 RTEN, 1,
 304                 , 3,
 305                 PWDA, 1,
 306         }
 307
 308         Scope(\_SB) {
 309                 /* PCIe Configuration Space for 16 busses */
 310                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 311                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 312                         /* Byte offsets are computed using the following technique:
 313                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 314                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 315                         */
 316                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 317                         STB5, 32,
 318                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 319                         PT0D, 1,
 320                         PT1D, 1,
 321                         PT2D, 1,
 322                         PT3D, 1,
 323                         PT4D, 1,
 324                         PT5D, 1,
 325                         PT6D, 1,
 326                         PT7D, 1,
 327                         PT8D, 1,
 328                         PT9D, 1,
 329                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 330                         SBIE, 1,
 331                         SBME, 1,
 332                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 333                         SBRI, 8,
 334                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 335                         SBB1, 32,
 336                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 337                         ,14,
 338                         P92E, 1,                /* Port92 decode enable */
 339                 }
 340
 341                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 342                         Field(SB5, AnyAcc, NoLock, Preserve){
 343                         /* Port 0 */
 344                         Offset(0x120),          /* Port 0 Task file status */
 345                         P0ER, 1,
 346                         , 2,
 347                         P0DQ, 1,
 348                         , 3,
 349                         P0BY, 1,
 350                         Offset(0x128),          /* Port 0 Serial ATA status */
 351                         P0DD, 4,
 352                         , 4,
 353                         P0IS, 4,
 354                         Offset(0x12C),          /* Port 0 Serial ATA control */
 355                         P0DI, 4,
 356                         Offset(0x130),          /* Port 0 Serial ATA error */
 357                         , 16,
 358                         P0PR, 1,
 359
 360                         /* Port 1 */
 361                         offset(0x1A0),          /* Port 1 Task file status */
 362                         P1ER, 1,
 363                         , 2,
 364                         P1DQ, 1,
 365                         , 3,
 366                         P1BY, 1,
 367                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 368                         P1DD, 4,
 369                         , 4,
 370                         P1IS, 4,
 371                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 372                         P1DI, 4,
 373                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 374                         , 16,
 375                         P1PR, 1,
 376
 377                         /* Port 2 */
 378                         Offset(0x220),          /* Port 2 Task file status */
 379                         P2ER, 1,
 380                         , 2,
 381                         P2DQ, 1,
 382                         , 3,
 383                         P2BY, 1,
 384                         Offset(0x228),          /* Port 2 Serial ATA status */
 385                         P2DD, 4,
 386                         , 4,
 387                         P2IS, 4,
 388                         Offset(0x22C),          /* Port 2 Serial ATA control */
 389                         P2DI, 4,
 390                         Offset(0x230),          /* Port 2 Serial ATA error */
 391                         , 16,
 392                         P2PR, 1,
 393
 394                         /* Port 3 */
 395                         Offset(0x2A0),          /* Port 3 Task file status */
 396                         P3ER, 1,
 397                         , 2,
 398                         P3DQ, 1,
 399                         , 3,
 400                         P3BY, 1,
 401                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 402                         P3DD, 4,
 403                         , 4,
 404                         P3IS, 4,
 405                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 406                         P3DI, 4,
 407                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 408                         , 16,
 409                         P3PR, 1,
 410                 }
 411         }
 412
 413
 414         #include "acpi/routing.asl"
 415
 416         Scope(\_SB) {
 417
 418                 Method(CkOT, 0){
 419
 420                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
 421
 422                         if(CondRefOf(\_OSI,Local1))
 423                         {
 424                                 Store(1, OSTP)                /* Assume some form of XP */
 425                                 if (\_OSI("Windows 2006"))      /* Vista */
 426                                 {
 427                                         Store(2, OSTP)
 428                                 }
 429                         } else {
 430                                 If(WCMP(\_OS,"Linux")) {
 431                                         Store(3, OSTP)            /* Linux */
 432                                 } Else {
 433                                         Store(4, OSTP)            /* Gotta be WinCE */
 434                                 }
 435                         }
 436                         Return(OSTP)
 437                 }
 438
 439                 Method(_PIC, 0x01, NotSerialized)
 440                 {
 441                         If (Arg0)
 442                         {
 443                                 \_SB.CIRQ()
 444                         }
 445                         Store(Arg0, PMOD)
 446                 }
 447                 Method(CIRQ, 0x00, NotSerialized){
 448                         Store(0, PINA)
 449                         Store(0, PINB)
 450                         Store(0, PINC)
 451                         Store(0, PIND)
 452                         Store(0, PINE)
 453                         Store(0, PINF)
 454                         Store(0, PING)
 455                         Store(0, PINH)
 456                 }
 457
 458                 Name(IRQB, ResourceTemplate(){
 459                         IRQ(Level,ActiveLow,Shared){15}
 460                 })
 461
 462                 Name(IRQP, ResourceTemplate(){
 463                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
 464                 })
 465
 466                 Name(PITF, ResourceTemplate(){
 467                         IRQ(Level,ActiveLow,Exclusive){9}
 468                 })
 469
 470                 Device(INTA) {
 471                         Name(_HID, EISAID("PNP0C0F"))
 472                         Name(_UID, 1)
 473
 474                         Method(_STA, 0) {
 475                                 if (PINA) {
 476                                         Return(0x0B) /* sata is invisible */
 477                                 } else {
 478                                         Return(0x09) /* sata is disabled */
 479                                 }
 480                         } /* End Method(_SB.INTA._STA) */
 481
 482                         Method(_DIS ,0) {
 483                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
 484                                 Store(0, PINA)
 485                         } /* End Method(_SB.INTA._DIS) */
 486
 487                         Method(_PRS ,0) {
 488                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
 489                                 Return(IRQP)
 490                         } /* Method(_SB.INTA._PRS) */
 491
 492                         Method(_CRS ,0) {
 493                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 494                                 CreateWordField(IRQB, 0x1, IRQN)
 495                                 ShiftLeft(1, PINA, IRQN)
 496                                 Return(IRQB)
 497                         } /* Method(_SB.INTA._CRS) */
 498
 499                         Method(_SRS, 1) {
 500                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 501                                 CreateWordField(ARG0, 1, IRQM)
 502
 503                                 /* Use lowest available IRQ */
 504                                 FindSetRightBit(IRQM, Local0)
 505                                 if (Local0) {
 506                                         Decrement(Local0)
 507                                 }
 508                                 Store(Local0, PINA)
 509                         } /* End Method(_SB.INTA._SRS) */
 510                 } /* End Device(INTA) */
 511
 512                 Device(INTB) {
 513                         Name(_HID, EISAID("PNP0C0F"))
 514                         Name(_UID, 2)
 515
 516                         Method(_STA, 0) {
 517                                 if (PINB) {
 518                                         Return(0x0B) /* sata is invisible */
 519                                 } else {
 520                                         Return(0x09) /* sata is disabled */
 521                                 }
 522                         } /* End Method(_SB.INTB._STA) */
 523
 524                         Method(_DIS ,0) {
 525                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
 526                                 Store(0, PINB)
 527                         } /* End Method(_SB.INTB._DIS) */
 528
 529                         Method(_PRS ,0) {
 530                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
 531                                 Return(IRQP)
 532                         } /* Method(_SB.INTB._PRS) */
 533
 534                         Method(_CRS ,0) {
 535                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 536                                 CreateWordField(IRQB, 0x1, IRQN)
 537                                 ShiftLeft(1, PINB, IRQN)
 538                                 Return(IRQB)
 539                         } /* Method(_SB.INTB._CRS) */
 540
 541                         Method(_SRS, 1) {
 542                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 543                                 CreateWordField(ARG0, 1, IRQM)
 544
 545                                 /* Use lowest available IRQ */
 546                                 FindSetRightBit(IRQM, Local0)
 547                                 if (Local0) {
 548                                         Decrement(Local0)
 549                                 }
 550                                 Store(Local0, PINB)
 551                         } /* End Method(_SB.INTB._SRS) */
 552                 } /* End Device(INTB)  */
 553
 554                 Device(INTC) {
 555                         Name(_HID, EISAID("PNP0C0F"))
 556                         Name(_UID, 3)
 557
 558                         Method(_STA, 0) {
 559                                 if (PINC) {
 560                                         Return(0x0B) /* sata is invisible */
 561                                 } else {
 562                                         Return(0x09) /* sata is disabled */
 563                                 }
 564                         } /* End Method(_SB.INTC._STA) */
 565
 566                         Method(_DIS ,0) {
 567                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
 568                                 Store(0, PINC)
 569                         } /* End Method(_SB.INTC._DIS) */
 570
 571                         Method(_PRS ,0) {
 572                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
 573                                 Return(IRQP)
 574                         } /* Method(_SB.INTC._PRS) */
 575
 576                         Method(_CRS ,0) {
 577                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 578                                 CreateWordField(IRQB, 0x1, IRQN)
 579                                 ShiftLeft(1, PINC, IRQN)
 580                                 Return(IRQB)
 581                         } /* Method(_SB.INTC._CRS) */
 582
 583                         Method(_SRS, 1) {
 584                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 585                                 CreateWordField(ARG0, 1, IRQM)
 586
 587                                 /* Use lowest available IRQ */
 588                                 FindSetRightBit(IRQM, Local0)
 589                                 if (Local0) {
 590                                         Decrement(Local0)
 591                                 }
 592                                 Store(Local0, PINC)
 593                         } /* End Method(_SB.INTC._SRS) */
 594                 } /* End Device(INTC)  */
 595
 596                 Device(INTD) {
 597                         Name(_HID, EISAID("PNP0C0F"))
 598                         Name(_UID, 4)
 599
 600                         Method(_STA, 0) {
 601                                 if (PIND) {
 602                                         Return(0x0B) /* sata is invisible */
 603                                 } else {
 604                                         Return(0x09) /* sata is disabled */
 605                                 }
 606                         } /* End Method(_SB.INTD._STA) */
 607
 608                         Method(_DIS ,0) {
 609                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
 610                                 Store(0, PIND)
 611                         } /* End Method(_SB.INTD._DIS) */
 612
 613                         Method(_PRS ,0) {
 614                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
 615                                 Return(IRQP)
 616                         } /* Method(_SB.INTD._PRS) */
 617
 618                         Method(_CRS ,0) {
 619                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 620                                 CreateWordField(IRQB, 0x1, IRQN)
 621                                 ShiftLeft(1, PIND, IRQN)
 622                                 Return(IRQB)
 623                         } /* Method(_SB.INTD._CRS) */
 624
 625                         Method(_SRS, 1) {
 626                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 627                                 CreateWordField(ARG0, 1, IRQM)
 628
 629                                 /* Use lowest available IRQ */
 630                                 FindSetRightBit(IRQM, Local0)
 631                                 if (Local0) {
 632                                         Decrement(Local0)
 633                                 }
 634                                 Store(Local0, PIND)
 635                         } /* End Method(_SB.INTD._SRS) */
 636                 } /* End Device(INTD)  */
 637
 638                 Device(INTE) {
 639                         Name(_HID, EISAID("PNP0C0F"))
 640                         Name(_UID, 5)
 641
 642                         Method(_STA, 0) {
 643                                 if (PINE) {
 644                                         Return(0x0B) /* sata is invisible */
 645                                 } else {
 646                                         Return(0x09) /* sata is disabled */
 647                                 }
 648                         } /* End Method(_SB.INTE._STA) */
 649
 650                         Method(_DIS ,0) {
 651                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
 652                                 Store(0, PINE)
 653                         } /* End Method(_SB.INTE._DIS) */
 654
 655                         Method(_PRS ,0) {
 656                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
 657                                 Return(IRQP)
 658                         } /* Method(_SB.INTE._PRS) */
 659
 660                         Method(_CRS ,0) {
 661                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 662                                 CreateWordField(IRQB, 0x1, IRQN)
 663                                 ShiftLeft(1, PINE, IRQN)
 664                                 Return(IRQB)
 665                         } /* Method(_SB.INTE._CRS) */
 666
 667                         Method(_SRS, 1) {
 668                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 669                                 CreateWordField(ARG0, 1, IRQM)
 670
 671                                 /* Use lowest available IRQ */
 672                                 FindSetRightBit(IRQM, Local0)
 673                                 if (Local0) {
 674                                         Decrement(Local0)
 675                                 }
 676                                 Store(Local0, PINE)
 677                         } /* End Method(_SB.INTE._SRS) */
 678                 } /* End Device(INTE)  */
 679
 680                 Device(INTF) {
 681                         Name(_HID, EISAID("PNP0C0F"))
 682                         Name(_UID, 6)
 683
 684                         Method(_STA, 0) {
 685                                 if (PINF) {
 686                                         Return(0x0B) /* sata is invisible */
 687                                 } else {
 688                                         Return(0x09) /* sata is disabled */
 689                                 }
 690                         } /* End Method(_SB.INTF._STA) */
 691
 692                         Method(_DIS ,0) {
 693                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
 694                                 Store(0, PINF)
 695                         } /* End Method(_SB.INTF._DIS) */
 696
 697                         Method(_PRS ,0) {
 698                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
 699                                 Return(PITF)
 700                         } /* Method(_SB.INTF._PRS) */
 701
 702                         Method(_CRS ,0) {
 703                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 704                                 CreateWordField(IRQB, 0x1, IRQN)
 705                                 ShiftLeft(1, PINF, IRQN)
 706                                 Return(IRQB)
 707                         } /* Method(_SB.INTF._CRS) */
 708
 709                         Method(_SRS, 1) {
 710                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 711                                 CreateWordField(ARG0, 1, IRQM)
 712
 713                                 /* Use lowest available IRQ */
 714                                 FindSetRightBit(IRQM, Local0)
 715                                 if (Local0) {
 716                                         Decrement(Local0)
 717                                 }
 718                                 Store(Local0, PINF)
 719                         } /*  End Method(_SB.INTF._SRS) */
 720                 } /* End Device(INTF)  */
 721
 722                 Device(INTG) {
 723                         Name(_HID, EISAID("PNP0C0F"))
 724                         Name(_UID, 7)
 725
 726                         Method(_STA, 0) {
 727                                 if (PING) {
 728                                         Return(0x0B) /* sata is invisible */
 729                                 } else {
 730                                         Return(0x09) /* sata is disabled */
 731                                 }
 732                         } /* End Method(_SB.INTG._STA)  */
 733
 734                         Method(_DIS ,0) {
 735                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
 736                                 Store(0, PING)
 737                         } /* End Method(_SB.INTG._DIS)  */
 738
 739                         Method(_PRS ,0) {
 740                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
 741                                 Return(IRQP)
 742                         } /* Method(_SB.INTG._CRS)  */
 743
 744                         Method(_CRS ,0) {
 745                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 746                                 CreateWordField(IRQB, 0x1, IRQN)
 747                                 ShiftLeft(1, PING, IRQN)
 748                                 Return(IRQB)
 749                         } /* Method(_SB.INTG._CRS)  */
 750
 751                         Method(_SRS, 1) {
 752                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 753                                 CreateWordField(ARG0, 1, IRQM)
 754
 755                                 /* Use lowest available IRQ */
 756                                 FindSetRightBit(IRQM, Local0)
 757                                 if (Local0) {
 758                                         Decrement(Local0)
 759                                 }
 760                                 Store(Local0, PING)
 761                         } /* End Method(_SB.INTG._SRS)  */
 762                 } /* End Device(INTG)  */
 763
 764                 Device(INTH) {
 765                         Name(_HID, EISAID("PNP0C0F"))
 766                         Name(_UID, 8)
 767
 768                         Method(_STA, 0) {
 769                                 if (PINH) {
 770                                         Return(0x0B) /* sata is invisible */
 771                                 } else {
 772                                         Return(0x09) /* sata is disabled */
 773                                 }
 774                         } /* End Method(_SB.INTH._STA)  */
 775
 776                         Method(_DIS ,0) {
 777                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
 778                                 Store(0, PINH)
 779                         } /* End Method(_SB.INTH._DIS)  */
 780
 781                         Method(_PRS ,0) {
 782                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
 783                                 Return(IRQP)
 784                         } /* Method(_SB.INTH._CRS)  */
 785
 786                         Method(_CRS ,0) {
 787                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 788                                 CreateWordField(IRQB, 0x1, IRQN)
 789                                 ShiftLeft(1, PINH, IRQN)
 790                                 Return(IRQB)
 791                         } /* Method(_SB.INTH._CRS)  */
 792
 793                         Method(_SRS, 1) {
 794                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 795                                 CreateWordField(ARG0, 1, IRQM)
 796
 797                                 /* Use lowest available IRQ */
 798                                 FindSetRightBit(IRQM, Local0)
 799                                 if (Local0) {
 800                                         Decrement(Local0)
 801                                 }
 802                                 Store(Local0, PINH)
 803                         } /* End Method(_SB.INTH._SRS)  */
 804                 } /* End Device(INTH)   */
 805
 806         }   /* End Scope(_SB)  */
 807
 808
 809         /* Supported sleep states: */
 810         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 811
 812         If (LAnd(SSFG, 0x01)) {
 813                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 814         }
 815         If (LAnd(SSFG, 0x02)) {
 816                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 817         }
 818         If (LAnd(SSFG, 0x04)) {
 819                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 820         }
 821         If (LAnd(SSFG, 0x08)) {
 822                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 823         }
 824
 825         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 826
 827         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 828         Name(CSMS, 0)                   /* Current System State */
 829
 830         /* Wake status package */
 831         Name(WKST,Package(){Zero, Zero})
 832
 833         /*
 834         * \_PTS - Prepare to Sleep method
 835         *
 836         *       Entry:
 837         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 838         *
 839         * Exit:
 840         *               -none-
 841         *
 842         * The _PTS control method is executed at the beginning of the sleep process
 843         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 844         * control method may be executed a relatively long time before entering the
 845         * sleep state and the OS may abort      the operation without notification to
 846         * the ACPI driver.  This method cannot modify the configuration or power
 847         * state of any device in the system.
 848         */
 849         Method(\_PTS, 1) {
 850                 /* DBGO("\\_PTS\n") */
 851                 /* DBGO("From S0 to S") */
 852                 /* DBGO(Arg0) */
 853                 /* DBGO("\n") */
 854
 855                 /* Don't allow PCIRST# to reset USB */
 856                 if (LEqual(Arg0,3)){
 857                         Store(0,URRE)
 858                 }
 859
 860                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 861                 /*Store(One, CSSM)
 862                 Store(One, SSEN)*/
 863
 864                 /* On older chips, clear PciExpWakeDisEn */
 865                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 866                 *       Store(0,\_SB.PWDE)
 867                 *}
 868                 */
 869
 870                 /* Clear wake status structure. */
 871                 Store(0, Index(WKST,0))
 872                 Store(0, Index(WKST,1))
 873                 \_SB.PCI0.SIOS (Arg0)
 874         } /* End Method(\_PTS) */
 875
 876         /*
 877         *  The following method results in a "not a valid reserved NameSeg"
 878         *  warning so I have commented it out for the duration.  It isn't
 879         *  used, so it could be removed.
 880         *
 881         *
 882         *       \_GTS OEM Going To Sleep method
 883         *
 884         *       Entry:
 885         *               Arg0=The value of the sleeping state S1=1, S2=2
 886         *
 887         *       Exit:
 888         *               -none-
 889         *
 890         *  Method(\_GTS, 1) {
 891         *  DBGO("\\_GTS\n")
 892         *  DBGO("From S0 to S")
 893         *  DBGO(Arg0)
 894         *  DBGO("\n")
 895         *  }
 896         */
 897
 898         /*
 899         *       \_BFS OEM Back From Sleep method
 900         *
 901         *       Entry:
 902         *               Arg0=The value of the sleeping state S1=1, S2=2
 903         *
 904         *       Exit:
 905         *               -none-
 906         */
 907         Method(\_BFS, 1) {
 908                 /* DBGO("\\_BFS\n") */
 909                 /* DBGO("From S") */
 910                 /* DBGO(Arg0) */
 911                 /* DBGO(" to S0\n") */
 912         }
 913
 914         /*
 915         *  \_WAK System Wake method
 916         *
 917         *       Entry:
 918         *               Arg0=The value of the sleeping state S1=1, S2=2
 919         *
 920         *       Exit:
 921         *               Return package of 2 DWords
 922         *               Dword 1 - Status
 923         *                       0x00000000      wake succeeded
 924         *                       0x00000001      Wake was signaled but failed due to lack of power
 925         *                       0x00000002      Wake was signaled but failed due to thermal condition
 926         *               Dword 2 - Power Supply state
 927         *                       if non-zero the effective S-state the power supply entered
 928         */
 929         Method(\_WAK, 1) {
 930                 /* DBGO("\\_WAK\n") */
 931                 /* DBGO("From S") */
 932                 /* DBGO(Arg0) */
 933                 /* DBGO(" to S0\n") */
 934
 935                 /* Re-enable HPET */
 936                 Store(1,HPDE)
 937
 938                 /* Restore PCIRST# so it resets USB */
 939                 if (LEqual(Arg0,3)){
 940                         Store(1,URRE)
 941                 }
 942
 943                 /* Arbitrarily clear PciExpWakeStatus */
 944                 Store(PWST, PWST)
 945
 946                 /* if(DeRefOf(Index(WKST,0))) {
 947                 *       Store(0, Index(WKST,1))
 948                 * } else {
 949                 *       Store(Arg0, Index(WKST,1))
 950                 * }
 951                 */
 952                 \_SB.PCI0.SIOW (Arg0)
 953                 Return(WKST)
 954         } /* End Method(\_WAK) */
 955
 956         Scope(\_GPE) {  /* Start Scope GPE */
 957                 /*  General event 0  */
 958                 /* Method(_L00) {
 959                 *       DBGO("\\_GPE\\_L00\n")
 960                 * }
 961                 */
 962
 963                 /*  General event 1  */
 964                 /* Method(_L01) {
 965                 *       DBGO("\\_GPE\\_L00\n")
 966                 * }
 967                 */
 968
 969                 /*  General event 2  */
 970                 /* Method(_L02) {
 971                 *       DBGO("\\_GPE\\_L00\n")
 972                 * }
 973                 */
 974
 975                 /*  General event 3  */
 976                 Method(_L03) {
 977                         /* DBGO("\\_GPE\\_L00\n") */
 978                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 979                 }
 980
 981                 /*  General event 4  */
 982                 /* Method(_L04) {
 983                 *       DBGO("\\_GPE\\_L00\n")
 984                 * }
 985                 */
 986
 987                 /*  General event 5  */
 988                 /* Method(_L05) {
 989                 *       DBGO("\\_GPE\\_L00\n")
 990                 * }
 991                 */
 992
 993                 /*  General event 6 - Used for GPM6, moved to USB.asl */
 994                 /* Method(_L06) {
 995                 *       DBGO("\\_GPE\\_L00\n")
 996                 * }
 997                 */
 998
 999                 /*  General event 7 - Used for GPM7, moved to USB.asl */
1000                 /* Method(_L07) {
1001                 *       DBGO("\\_GPE\\_L07\n")
1002                 * }
1003                 */
1004
1005                 /*  Legacy PM event  */
1006                 Method(_L08) {
1007                         /* DBGO("\\_GPE\\_L08\n") */
1008                 }
1009
1010                 /*  Temp warning (TWarn) event  */
1011                 Method(_L09) {
1012                         /* DBGO("\\_GPE\\_L09\n") */
1013                         Notify (\_TZ.TZ00, 0x80)
1014                 }
1015
1016                 /*  Reserved  */
1017                 /* Method(_L0A) {
1018                 *       DBGO("\\_GPE\\_L0A\n")
1019                 * }
1020                 */
1021
1022                 /*  USB controller PME#  */
1023                 Method(_L0B) {
1024                         /* DBGO("\\_GPE\\_L0B\n") */
1025                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1026                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1027                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1028                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1029                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1030                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1031                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1032                 }
1033
1034                 /*  AC97 controller PME#  */
1035                 /* Method(_L0C) {
1036                 *       DBGO("\\_GPE\\_L0C\n")
1037                 * }
1038                 */
1039
1040                 /*  OtherTherm PME#  */
1041                 /* Method(_L0D) {
1042                 *       DBGO("\\_GPE\\_L0D\n")
1043                 * }
1044                 */
1045
1046                 /*  GPM9 SCI event - Moved to USB.asl */
1047                 /* Method(_L0E) {
1048                 *       DBGO("\\_GPE\\_L0E\n")
1049                 * }
1050                 */
1051
1052                 /*  PCIe HotPlug event  */
1053                 /* Method(_L0F) {
1054                 *       DBGO("\\_GPE\\_L0F\n")
1055                 * }
1056                 */
1057
1058                 /*  ExtEvent0 SCI event  */
1059                 Method(_L10) {
1060                         /* DBGO("\\_GPE\\_L10\n") */
1061                 }
1062
1063
1064                 /*  ExtEvent1 SCI event  */
1065                 Method(_L11) {
1066                         /* DBGO("\\_GPE\\_L11\n") */
1067                 }
1068
1069                 /*  PCIe PME# event  */
1070                 /* Method(_L12) {
1071                 *       DBGO("\\_GPE\\_L12\n")
1072                 * }
1073                 */
1074
1075                 /*  GPM0 SCI event - Moved to USB.asl */
1076                 /* Method(_L13) {
1077                 *       DBGO("\\_GPE\\_L13\n")
1078                 * }
1079                 */
1080
1081                 /*  GPM1 SCI event - Moved to USB.asl */
1082                 /* Method(_L14) {
1083                 *       DBGO("\\_GPE\\_L14\n")
1084                 * }
1085                 */
1086
1087                 /*  GPM2 SCI event - Moved to USB.asl */
1088                 /* Method(_L15) {
1089                 *       DBGO("\\_GPE\\_L15\n")
1090                 * }
1091                 */
1092
1093                 /*  GPM3 SCI event - Moved to USB.asl */
1094                 /* Method(_L16) {
1095                 *       DBGO("\\_GPE\\_L16\n")
1096                 * }
1097                 */
1098
1099                 /*  GPM8 SCI event - Moved to USB.asl */
1100                 /* Method(_L17) {
1101                 *       DBGO("\\_GPE\\_L17\n")
1102                 * }
1103                 */
1104
1105                 /*  GPIO0 or GEvent8 event  */
1106                 Method(_L18) {
1107                         /* DBGO("\\_GPE\\_L18\n") */
1108                         Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1109                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1110                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1111                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1112                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1113                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1114                 }
1115
1116                 /*  GPM4 SCI event - Moved to USB.asl */
1117                 /* Method(_L19) {
1118                 *       DBGO("\\_GPE\\_L19\n")
1119                 * }
1120                 */
1121
1122                 /*  GPM5 SCI event - Moved to USB.asl */
1123                 /* Method(_L1A) {
1124                 *       DBGO("\\_GPE\\_L1A\n")
1125                 * }
1126                 */
1127
1128                 /*  Azalia SCI event  */
1129                 Method(_L1B) {
1130                         /* DBGO("\\_GPE\\_L1B\n") */
1131                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1132                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1133                 }
1134
1135                 /*  GPM6 SCI event - Reassigned to _L06 */
1136                 /* Method(_L1C) {
1137                 *       DBGO("\\_GPE\\_L1C\n")
1138                 * }
1139                 */
1140
1141                 /*  GPM7 SCI event - Reassigned to _L07 */
1142                 /* Method(_L1D) {
1143                 *       DBGO("\\_GPE\\_L1D\n")
1144                 * }
1145                 */
1146
1147                 /*  GPIO2 or GPIO66 SCI event  */
1148                 /* Method(_L1E) {
1149                 *       DBGO("\\_GPE\\_L1E\n")
1150                 * }
1151                 */
1152
1153                 /*  SATA SCI event - Moved to sata.asl */
1154                 /* Method(_L1F) {
1155                 *        DBGO("\\_GPE\\_L1F\n")
1156                 * }
1157                 */
1158
1159         }       /* End Scope GPE */
1160
1161         #include "acpi/usb.asl"
1162
1163         /* South Bridge */
1164         Scope(\_SB) { /* Start \_SB scope */
1165                 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1166
1167                 /*  _SB.PCI0 */
1168                 /* Note: Only need HID on Primary Bus */
1169                 Device(PCI0) {
1170                         External (TOM1)
1171                         External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1172                         Name(_HID, EISAID("PNP0A03"))
1173                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1174                         Method(_BBN, 0) { /* Bus number = 0 */
1175                                 Return(0)
1176                         }
1177                         Method(_STA, 0) {
1178                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1179                                 Return(0x0B)     /* Status is visible */
1180                         }
1181
1182                         Method(_PRT,0) {
1183                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1184                                 Return (PR0)                  /* PIC Mode */
1185                         } /* end _PRT */
1186
1187                         /* Describe the Northbridge devices */
1188                         Device(AMRT) {
1189                                 Name(_ADR, 0x00000000)
1190                         } /* end AMRT */
1191
1192                         /* The internal GFX bridge */
1193                         Device(AGPB) {
1194                                 Name(_ADR, 0x00010000)
1195                                 Name(_PRW, Package() {0x18, 4})
1196                                 Method(_PRT,0) {
1197                                         Return (APR1)
1198                                 }
1199                         }  /* end AGPB */
1200
1201                         /* The external GFX bridge */
1202                         Device(PBR2) {
1203                                 Name(_ADR, 0x00020000)
1204                                 Name(_PRW, Package() {0x18, 4})
1205                                 Method(_PRT,0) {
1206                                         If(PMOD){ Return(APS2) }   /* APIC mode */
1207                                         Return (PS2)                  /* PIC Mode */
1208                                 } /* end _PRT */
1209                         } /* end PBR2 */
1210
1211                         /* Dev3 is also an external GFX bridge, not used in Herring */
1212
1213                         Device(PBR4) {
1214                                 Name(_ADR, 0x00040000)
1215                                 Name(_PRW, Package() {0x18, 4})
1216                                 Method(_PRT,0) {
1217                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1218                                         Return (PS4)                  /* PIC Mode */
1219                                 } /* end _PRT */
1220                         } /* end PBR4 */
1221
1222                         Device(PBR5) {
1223                                 Name(_ADR, 0x00050000)
1224                                 Name(_PRW, Package() {0x18, 4})
1225                                 Method(_PRT,0) {
1226                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1227                                         Return (PS5)                  /* PIC Mode */
1228                                 } /* end _PRT */
1229                         } /* end PBR5 */
1230
1231                         Device(PBR6) {
1232                                 Name(_ADR, 0x00060000)
1233                                 Name(_PRW, Package() {0x18, 4})
1234                                 Method(_PRT,0) {
1235                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1236                                         Return (PS6)                  /* PIC Mode */
1237                                 } /* end _PRT */
1238                         } /* end PBR6 */
1239
1240                         /* The onboard EtherNet chip */
1241                         Device(PBR7) {
1242                                 Name(_ADR, 0x00070000)
1243                                 Name(_PRW, Package() {0x18, 4})
1244                                 Method(_PRT,0) {
1245                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1246                                         Return (PS7)                  /* PIC Mode */
1247                                 } /* end _PRT */
1248                         } /* end PBR7 */
1249
1250                         /* GPP */
1251                         Device(PBR9) {
1252                                 Name(_ADR, 0x00090000)
1253                                 Name(_PRW, Package() {0x18, 4})
1254                                 Method(_PRT,0) {
1255                                         If(PMOD){ Return(APS9) }   /* APIC mode */
1256                                         Return (PS9)                  /* PIC Mode */
1257                                 } /* end _PRT */
1258                         } /* end PBR9 */
1259
1260                         Device(PBRa) {
1261                                 Name(_ADR, 0x000A0000)
1262                                 Name(_PRW, Package() {0x18, 4})
1263                                 Method(_PRT,0) {
1264                                         If(PMOD){ Return(APSa) }   /* APIC mode */
1265                                         Return (PSa)                  /* PIC Mode */
1266                                 } /* end _PRT */
1267                         } /* end PBRa */
1268
1269
1270                         /* PCI slot 1, 2, 3 */
1271                         Device(PIBR) {
1272                                 Name(_ADR, 0x00140004)
1273                                 Name(_PRW, Package() {0x18, 4})
1274
1275                                 Method(_PRT, 0) {
1276                                         Return (PCIB)
1277                                 }
1278                         }
1279
1280                         /* Describe the Southbridge devices */
1281                         Device(STCR) {
1282                                 Name(_ADR, 0x00110000)
1283                                 #include "acpi/sata.asl"
1284                         } /* end STCR */
1285
1286                         Device(UOH1) {
1287                                 Name(_ADR, 0x00130000)
1288                                 Name(_PRW, Package() {0x0B, 3})
1289                         } /* end UOH1 */
1290
1291                         Device(UOH2) {
1292                                 Name(_ADR, 0x00130001)
1293                                 Name(_PRW, Package() {0x0B, 3})
1294                         } /* end UOH2 */
1295
1296                         Device(UOH3) {
1297                                 Name(_ADR, 0x00130002)
1298                                 Name(_PRW, Package() {0x0B, 3})
1299                         } /* end UOH3 */
1300
1301                         Device(UOH4) {
1302                                 Name(_ADR, 0x00130003)
1303                                 Name(_PRW, Package() {0x0B, 3})
1304                         } /* end UOH4 */
1305
1306                         Device(UOH5) {
1307                                 Name(_ADR, 0x00130004)
1308                                 Name(_PRW, Package() {0x0B, 3})
1309                         } /* end UOH5 */
1310
1311                         Device(UEH1) {
1312                                 Name(_ADR, 0x00130005)
1313                                 Name(_PRW, Package() {0x0B, 3})
1314                         } /* end UEH1 */
1315
1316                         Device(SBUS) {
1317                                 Name(_ADR, 0x00140000)
1318                         } /* end SBUS */
1319
1320                         /* Primary (and only) IDE channel */
1321                         Device(IDEC) {
1322                                 Name(_ADR, 0x00140001)
1323                                 #include "acpi/ide.asl"
1324                         } /* end IDEC */
1325
1326                         Device(AZHD) {
1327                                 Name(_ADR, 0x00140002)
1328                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1329                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1330                                         offset (0x42),
1331                                         NSDI, 1,
1332                                         NSDO, 1,
1333                                         NSEN, 1,
1334                                         offset (0x44),
1335                                         IPCR, 4,
1336                                         offset (0x54),
1337                                         PWST, 2,
1338                                         , 6,
1339                                         PMEB, 1,
1340                                         , 6,
1341                                         PMST, 1,
1342                                         offset (0x62),
1343                                         MMCR, 1,
1344                                         offset (0x64),
1345                                         MMLA, 32,
1346                                         offset (0x68),
1347                                         MMHA, 32,
1348                                         offset (0x6C),
1349                                         MMDT, 16,
1350                                 }
1351
1352                                 Method(_INI) {
1353                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1354                                                 Store(zero, NSEN)
1355                                                 Store(one, NSDO)
1356                                                 Store(one, NSDI)
1357                                         }
1358                                 }
1359                         } /* end AZHD */
1360
1361                         Device(LIBR) {
1362                                 Name(_ADR, 0x00140003)
1363                                 /* Method(_INI) {
1364                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1365                                 } */ /* End Method(_SB.SBRDG._INI) */
1366
1367                                 /* Real Time Clock Device */
1368                                 Device(RTC0) {
1369                                         Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
1370                                         Name(_CRS, ResourceTemplate() {
1371                                                 IRQNoFlags(){8}
1372                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1373                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1374                                         })
1375                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1376
1377                                 Device(TMR) {   /* Timer */
1378                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1379                                         Name(_CRS, ResourceTemplate() {
1380                                                 IRQNoFlags(){0}
1381                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1382                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1383                                         })
1384                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1385
1386                                 Device(SPKR) {  /* Speaker */
1387                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1388                                         Name(_CRS, ResourceTemplate() {
1389                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1390                                         })
1391                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1392
1393                                 Device(PIC) {
1394                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1395                                         Name(_CRS, ResourceTemplate() {
1396                                                 IRQNoFlags(){2}
1397                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1398                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1399                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1400                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1401                                         })
1402                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1403
1404                                 Device(MAD) { /* 8257 DMA */
1405                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1406                                         Name(_CRS, ResourceTemplate() {
1407                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1408                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1409                                                 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1410                                                 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1411                                                 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1412                                                 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1413                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1414                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1415                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1416
1417                                 Device(COPR) {
1418                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1419                                         Name(_CRS, ResourceTemplate() {
1420                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1421                                                 IRQNoFlags(){13}
1422                                         })
1423                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1424
1425                                 Device(HPTM) {
1426                                         Name(_HID,EISAID("PNP0103"))
1427                                         Name(CRS,ResourceTemplate()     {
1428                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1429                                         })
1430                                         Method(_STA, 0) {
1431                                                 Return(0x0F) /* sata is visible */
1432                                         }
1433                                         Method(_CRS, 0) {
1434                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1435                                                 Store(HPBA, HPBA)
1436                                                 Return(CRS)
1437                                         }
1438                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1439                         } /* end LIBR */
1440
1441                         Device(HPBR) {
1442                                 Name(_ADR, 0x00140004)
1443                         } /* end HostPciBr */
1444
1445                         Device(ACAD) {
1446                                 Name(_ADR, 0x00140005)
1447                         } /* end Ac97audio */
1448
1449                         Device(ACMD) {
1450                                 Name(_ADR, 0x00140006)
1451                         } /* end Ac97modem */
1452
1453                         /* ITE8718 Support */
1454                         OperationRegion (IOID, SystemIO, 0x2E, 0x02)    /* sometimes it is 0x4E */
1455                                 Field (IOID, ByteAcc, NoLock, Preserve)
1456                                 {
1457                                         SIOI,   8,    SIOD,   8         /* 0x2E and 0x2F */
1458                                 }
1459
1460                         IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1461                         {
1462                                         Offset (0x07),
1463                                 LDN,    8,      /* Logical Device Number */
1464                                         Offset (0x20),
1465                                 CID1,   8,      /* Chip ID Byte 1, 0x87 */
1466                                 CID2,   8,      /* Chip ID Byte 2, 0x12 */
1467                                         Offset (0x30),
1468                                 ACTR,   8,      /* Function activate */
1469                                         Offset (0xF0),
1470                                 APC0,   8,      /* APC/PME Event Enable Register */
1471                                 APC1,   8,      /* APC/PME Status Register */
1472                                 APC2,   8,      /* APC/PME Control Register 1 */
1473                                 APC3,   8,      /* Environment Controller Special Configuration Register */
1474                                 APC4,   8       /* APC/PME Control Register 2 */
1475                         }
1476
1477                         /* Enter the 8718 MB PnP Mode */
1478                         Method (EPNP)
1479                         {
1480                                 Store(0x87, SIOI)
1481                                 Store(0x01, SIOI)
1482                                 Store(0x55, SIOI)
1483                                 Store(0x55, SIOI) /* 8718 magic number */
1484                         }
1485                         /* Exit the 8718 MB PnP Mode */
1486                         Method (XPNP)
1487                         {
1488                                 Store (0x02, SIOI)
1489                                 Store (0x02, SIOD)
1490                         }
1491                         /*
1492                          * Keyboard PME is routed to SB700 Gevent3. We can wake
1493                          * up the system by pressing the key.
1494                          */
1495                         Method (SIOS, 1)
1496                         {
1497                                 /* We only enable KBD PME for S5. */
1498                                 If (LLess (Arg0, 0x05))
1499                                 {
1500                                         EPNP()
1501                                         /* DBGO("8718F\n") */
1502
1503                                         Store (0x4, LDN)
1504                                         Store (One, ACTR)  /* Enable EC */
1505                                         /*
1506                                         Store (0x4, LDN)
1507                                         Store (0x04, APC4)
1508                                         */  /* falling edge. which mode? Not sure. */
1509
1510                                         Store (0x4, LDN)
1511                                         Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1512                                         Store (0x4, LDN)
1513                                         Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1514
1515                                         XPNP()
1516                                 }
1517                         }
1518                         Method (SIOW, 1)
1519                         {
1520                                 EPNP()
1521                                 Store (0x4, LDN)
1522                                 Store (Zero, APC0) /* disable keyboard PME */
1523                                 Store (0x4, LDN)
1524                                 Store (0xFF, APC1) /* clear keyboard PME status */
1525                                 XPNP()
1526                         }
1527
1528                         Name(CRES, ResourceTemplate() {
1529                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1530
1531                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1532                                         0x0000,                 /* address granularity */
1533                                         0x0000,                 /* range minimum */
1534                                         0x0CF7,                 /* range maximum */
1535                                         0x0000,                 /* translation */
1536                                         0x0CF8                  /* length */
1537                                 )
1538
1539                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1540                                         0x0000,                 /* address granularity */
1541                                         0x0D00,                 /* range minimum */
1542                                         0xFFFF,                 /* range maximum */
1543                                         0x0000,                 /* translation */
1544                                         0xF300                  /* length */
1545                                 )
1546
1547                                 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1548                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1549                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1550                                 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
1551
1552                                 /* DRAM Memory from 1MB to TopMem */
1553                                 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)   /* 1MB to TopMem */
1554
1555                                 /* BIOS space just below 4GB */
1556                                 DWORDMemory(
1557                                         ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1558                                         0x00,                   /* Granularity */
1559                                         0x00000000,             /* Min */
1560                                         0x00000000,             /* Max */
1561                                         0x00000000,             /* Translation */
1562                                         0x00000001,             /* Max-Min, RLEN */
1563                                         ,,
1564                                         PCBM
1565                                 )
1566
1567                                 /* DRAM memory from 4GB to TopMem2 */
1568                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1569                                         0x00000000,             /* Granularity */
1570                                         0x00000000,             /* Min */
1571                                         0x00000000,             /* Max */
1572                                         0x00000000,             /* Translation */
1573                                         0x00000001,             /* Max-Min, RLEN */
1574                                         ,,
1575                                         DMHI
1576                                 )
1577
1578                                 /* BIOS space just below 16EB */
1579                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1580                                         0x00000000,             /* Granularity */
1581                                         0x00000000,             /* Min */
1582                                         0x00000000,             /* Max */
1583                                         0x00000000,             /* Translation */
1584                                         0x00000001,             /* Max-Min, RLEN */
1585                                         ,,
1586                                         PEBM
1587                                 )
1588
1589                         }) /* End Name(_SB.PCI0.CRES) */
1590
1591                         Method(_CRS, 0) {
1592                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1593
1594                                 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1595                                 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1596                                 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1597                                 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1598                                 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1599                                 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1600
1601                                 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1602                                 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1603                                 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1604                                 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1605
1606                                 If(LGreater(LOMH, 0xC0000)){
1607                                         Store(0xC0000, EM1B)    /* Hole above C0000 and below E0000 */
1608                                         Subtract(LOMH, 0xC0000, EM1L)   /* subtract start, assumes allocation from C0000 going up */
1609                                 }
1610
1611                                 /* Set size of memory from 1MB to TopMem */
1612                                 Subtract(TOM1, 0x100000, DMLL)
1613
1614                                 /*
1615                                 * If(LNotEqual(TOM2, 0x00000000)){
1616                                 *       Store(0x100000000,DMHB)                 DRAM from 4GB to TopMem2
1617                                 *       ShiftLeft(TOM2, 20, Local0)
1618                                 *       Subtract(Local0, 0x100000000, DMHL)
1619                                 * }
1620                                 */
1621
1622                                 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1623                                 If(LEqual(TOM2, 0x00000000)){
1624                                         Store(PBAD,PBMB)                        /* Reserve the "BIOS" space */
1625                                         Store(PBLN,PBML)
1626                                 }
1627                                 Else {  /* Otherwise, put the BIOS just below 16EB */
1628                                         ShiftLeft(PBAD,16,EBMB)         /* Reserve the "BIOS" space */
1629                                         Store(PBLN,EBML)
1630                                 }
1631
1632                                 Return(CRES) /* note to change the Name buffer */
1633                         }  /* end of Method(_SB.PCI0._CRS) */
1634
1635                         /*
1636                         *
1637                         *               FIRST METHOD CALLED UPON BOOT
1638                         *
1639                         *  1. If debugging, print current OS and ACPI interpreter.
1640                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1641                         *     value is based on user choice in BIOS setup.
1642                         */
1643                         Method(_INI, 0) {
1644                                 /* DBGO("\\_SB\\_INI\n") */
1645                                 /* DBGO("   DSDT.ASL code from ") */
1646                                 /* DBGO(__DATE__) */
1647                                 /* DBGO(" ") */
1648                                 /* DBGO(__TIME__) */
1649                                 /* DBGO("\n   Sleep states supported: ") */
1650                                 /* DBGO("\n") */
1651                                 /* DBGO("   \\_OS=") */
1652                                 /* DBGO(\_OS) */
1653                                 /* DBGO("\n   \\_REV=") */
1654                                 /* DBGO(\_REV) */
1655                                 /* DBGO("\n") */
1656
1657                                 /* Determine the OS we're running on */
1658                                 CkOT()
1659
1660                                 /* On older chips, clear PciExpWakeDisEn */
1661                                 /*if (LLessEqual(\SBRI, 0x13)) {
1662                                 *       Store(0,\PWDE)
1663                                 * }
1664                                 */
1665                         } /* End Method(_SB._INI) */
1666                 } /* End Device(PCI0)  */
1667
1668                 Device(PWRB) {  /* Start Power button device */
1669                         Name(_HID, EISAID("PNP0C0C"))
1670                         Name(_UID, 0xAA)
1671                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1672                         Name(_STA, 0x0B) /* sata is invisible */
1673                 }
1674         } /* End \_SB scope */
1675
1676         Scope(\_SI) {
1677                 Method(_SST, 1) {
1678                         /* DBGO("\\_SI\\_SST\n") */
1679                         /* DBGO("   New Indicator state: ") */
1680                         /* DBGO(Arg0) */
1681                         /* DBGO("\n") */
1682                 }
1683         } /* End Scope SI */
1684
1685         /* SMBUS Support */
1686         Mutex (SBX0, 0x00)
1687         OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1688                 Field (SMB0, ByteAcc, NoLock, Preserve) {
1689                         HSTS,   8, /* SMBUS status */
1690                         SSTS,   8,  /* SMBUS slave status */
1691                         HCNT,   8,  /* SMBUS control */
1692                         HCMD,   8,  /* SMBUS host cmd */
1693                         HADD,   8,  /* SMBUS address */
1694                         DAT0,   8,  /* SMBUS data0 */
1695                         DAT1,   8,  /* SMBUS data1 */
1696                         BLKD,   8,  /* SMBUS block data */
1697                         SCNT,   8,  /* SMBUS slave control */
1698                         SCMD,   8,  /* SMBUS shaow cmd */
1699                         SEVT,   8,  /* SMBUS slave event */
1700                         SDAT,   8  /* SMBUS slave data */
1701         }
1702
1703         Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1704                 Store (0x1E, HSTS)
1705                 Store (0xFA, Local0)
1706                 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1707                         Stall (0x64)
1708                         Decrement (Local0)
1709                 }
1710
1711                 Return (Local0)
1712         }
1713
1714         Method (SWTC, 1, NotSerialized) {
1715                 Store (Arg0, Local0)
1716                 Store (0x07, Local2)
1717                 Store (One, Local1)
1718                 While (LEqual (Local1, One)) {
1719                         Store (And (HSTS, 0x1E), Local3)
1720                         If (LNotEqual (Local3, Zero)) { /* read sucess */
1721                                 If (LEqual (Local3, 0x02)) {
1722                                         Store (Zero, Local2)
1723                                 }
1724
1725                                 Store (Zero, Local1)
1726                         }
1727                         Else {
1728                                 If (LLess (Local0, 0x0A)) { /* read failure */
1729                                         Store (0x10, Local2)
1730                                         Store (Zero, Local1)
1731                                 }
1732                                 Else {
1733                                         Sleep (0x0A) /* 10 ms, try again */
1734                                         Subtract (Local0, 0x0A, Local0)
1735                                 }
1736                         }
1737                 }
1738
1739                 Return (Local2)
1740         }
1741
1742         Method (SMBR, 3, NotSerialized) {
1743                 Store (0x07, Local0)
1744                 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1745                         Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1746                         If (LEqual (Local0, Zero)) {
1747                                 Release (SBX0)
1748                                 Return (0x0)
1749                         }
1750
1751                         Store (0x1F, HSTS)
1752                         Store (Or (ShiftLeft (Arg1, One), One), HADD)
1753                         Store (Arg2, HCMD)
1754                         If (LEqual (Arg0, 0x07)) {
1755                                 Store (0x48, HCNT) /* read byte */
1756                         }
1757
1758                         Store (SWTC (0x03E8), Local1) /* 1000 ms */
1759                         If (LEqual (Local1, Zero)) {
1760                                 If (LEqual (Arg0, 0x07)) {
1761                                         Store (DAT0, Local0)
1762                                 }
1763                         }
1764                         Else {
1765                                 Store (Local1, Local0)
1766                         }
1767
1768                         Release (SBX0)
1769                 }
1770
1771                 /* DBGO("the value of SMBusData0 register ") */
1772                 /* DBGO(Arg2) */
1773                 /* DBGO(" is ") */
1774                 /* DBGO(Local0) */
1775                 /* DBGO("\n") */
1776
1777                 Return (Local0)
1778         }
1779
1780         /* THERMAL */
1781         Scope(\_TZ) {
1782                 Name (KELV, 2732)
1783                 Name (THOT, 800)
1784                 Name (TCRT, 850)
1785
1786                 ThermalZone(TZ00) {
1787                         Method(_AC0,0) {        /* Active Cooling 0 (0=highest fan speed) */
1788                                 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1789                                 Return(Add(0, 2730))
1790                         }
1791                         Method(_AL0,0) {        /* Returns package of cooling device to turn on */
1792                                 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1793                                 Return(Package() {\_TZ.TZ00.FAN0})
1794                         }
1795                         Device (FAN0) {
1796                                 Name(_HID, EISAID("PNP0C0B"))
1797                                 Name(_PR0, Package() {PFN0})
1798                         }
1799
1800                         PowerResource(PFN0,0,0) {
1801                                 Method(_STA) {
1802                                         Store(0xF,Local0)
1803                                         Return(Local0)
1804                                 }
1805                                 Method(_ON) {
1806                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1807                                 }
1808                                 Method(_OFF) {
1809                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1810                                 }
1811                         }
1812
1813                         Method(_HOT,0) {        /* return hot temp in tenths degree Kelvin */
1814                                 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1815                                 Return (Add (THOT, KELV))
1816                         }
1817                         Method(_CRT,0) {        /* return critical temp in tenths degree Kelvin */
1818                                 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1819                                 Return (Add (TCRT, KELV))
1820                         }
1821                         Method(_TMP,0) {        /* return current temp of this zone */
1822                                 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1823                                 If (LGreater (Local0, 0x10)) {
1824                                         Store (Local0, Local1)
1825                                 }
1826                                 Else {
1827                                         Add (Local0, THOT, Local0)
1828                                         Return (Add (400, KELV))
1829                                 }
1830
1831                                 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1832                                 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1833                                 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1834                                 If (LGreater (Local0, 0x10)) {
1835                                         If (LGreater (Local0, Local1)) {
1836                                                 Store (Local0, Local1)
1837                                         }
1838
1839                                         Multiply (Local1, 10, Local1)
1840                                         Return (Add (Local1, KELV))
1841                                 }
1842                                 Else {
1843                                         Add (Local0, THOT, Local0)
1844                                         Return (Add (400 , KELV))
1845                                 }
1846                         } /* end of _TMP */
1847                 } /* end of TZ00 */
1848         }
1849 }
1850 /* End of ASL file */