2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * ISA portions taken from QEMU acpi-dsdt.dsl.
25 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
27 #include "northbridge/amd/amdk8/amdk8_util.asl"
29 /* For now only define 2 power states:
30 * - S0 which is fully on
31 * - S5 which is soft off
32 * Any others would involve declaring the wake up methods.
34 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
35 Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 })
36 Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
39 /* blink a LED when entering the sleep (any type) */
40 Method (_PTS, 1, NotSerialized)
42 Store (0x1, \_SB.PCI0.ISA.LEDR)
45 /* cancel a LED blinking when waking from sleep (any type) */
46 Method (_WAK, 1, NotSerialized)
48 Store (0x0, \_SB.PCI0.ISA.LEDR)
50 Return(Package(0x02){0x00, 0x00})
53 /* Root of the bus hierarchy */
59 Name (_HID, EisaId ("PNP0A03"))
73 Method (_CRS, 0, NotSerialized)
75 Name (BUF0, ResourceTemplate ()
78 0x0CF8, // Address Range Minimum
79 0x0CF8, // Address Range Maximum
80 0x01, // Address Alignment
81 0x08, // Address Length
83 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
84 0x0000, // Address Space Granularity
85 0x0000, // Address Range Minimum
86 0x0CF7, // Address Range Maximum
87 0x0000, // Address Translation Offset
88 0x0CF8, // Address Length
91 /* Methods bellow use SSDT to get actual MMIO regs
92 The IO ports are from 0xd00, optionally an VGA,
93 otherwise the info from MMIO is used.
95 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
96 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
97 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
101 /* PCI Routing Table */
102 Name (_PRT, Package () {
103 Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
104 Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
105 Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
106 Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
107 Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
108 Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
109 Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
110 Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
111 Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
112 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
113 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
114 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
115 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
116 Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
117 Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
118 Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
119 Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
120 Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
121 Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
126 Name (_ADR, 0x00020000)
129 Name (_PRT, Package () {
130 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
131 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
132 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
133 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
139 Name (_ADR, 0x00030000)
142 Name (_PRT, Package () {
143 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
144 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
145 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
146 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
152 Name (_ADR, 0x00130000)
155 Name (_PRT, Package () {
156 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
157 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
158 Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
159 Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
165 Name (_ADR, 0x00130001)
168 Name (_PRT, Package () {
169 Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
170 Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
171 Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
172 Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
173 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
174 Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
175 Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
176 Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
180 Name (_ADR, 0x00110000)
181 OperationRegion (PCIC, PCI_Config, 0x0, 0xff)
182 Field (PCIC, ByteAcc, NoLock, Preserve)
185 /* two LSB bits are blink rate */
189 /* PS/2 keyboard (seems to be important for WinXP install) */
192 Name (_HID, EisaId ("PNP0303"))
193 Method (_STA, 0, NotSerialized)
197 Method (_CRS, 0, NotSerialized)
199 Name (TMP, ResourceTemplate () {
200 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
201 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
211 Name (_HID, EisaId ("PNP0F13"))
212 Method (_STA, 0, NotSerialized)
216 Method (_CRS, 0, NotSerialized)
218 Name (TMP, ResourceTemplate () {
225 /* PS/2 floppy controller */
228 Name (_HID, EisaId ("PNP0700"))
229 Method (_STA, 0, NotSerialized)
233 Method (_CRS, 0, NotSerialized)
235 Name (BUF0, ResourceTemplate () {
236 IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
237 IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
239 DMA (Compatibility, NotBusMaster, Transfer8) {2}