2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #if CONFIG_K8_REV_F_SUPPORT == 1
24 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
29 #include <device/pci_def.h>
30 #include <device/pci_ids.h>
32 #include <device/pnp_def.h>
33 #include <arch/romcc_io.h>
34 #include <cpu/x86/lapic.h>
35 #include <pc80/mc146818rtc.h>
36 #include <console/console.h>
38 #include <cpu/amd/model_fxx_rev.h>
39 #include "southbridge/nvidia/mcp55/early_smbus.c"
40 #include "northbridge/amd/amdk8/raminit.h"
41 #include "cpu/amd/model_fxx/apic_timer.c"
42 #include "lib/delay.c"
45 #include "cpu/x86/lapic/boot_cpu.c"
46 #include "northbridge/amd/amdk8/reset_test.c"
47 #include "superio/ite/it8716f/early_serial.c"
48 #include "superio/ite/it8716f/early_init.c"
49 #include "cpu/x86/bist.h"
50 #include "northbridge/amd/amdk8/debug.c"
51 #include "cpu/x86/mtrr/earlymtrr.c"
52 #include "northbridge/amd/amdk8/setup_resource_map.c"
53 #include "southbridge/nvidia/mcp55/early_ctrl.c"
55 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
57 static void memreset(int controllers, const struct mem_controller *ctrl) {}
58 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
60 static inline int spd_read_byte(unsigned int device, unsigned int address)
62 return smbus_read_byte(device, address);
65 #include "northbridge/amd/amdk8/f.h"
66 #include "northbridge/amd/amdk8/incoherent_ht.c"
67 #include "northbridge/amd/amdk8/coherent_ht.c"
68 #include "northbridge/amd/amdk8/raminit_f.c"
69 #include "lib/generic_sdram.c"
70 #include "resourcemap.c"
71 #include "cpu/amd/dualcore/dualcore.c"
72 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
73 #include "southbridge/nvidia/mcp55/early_setup_car.c"
74 #include "cpu/amd/car/post_cache_as_ram.c"
75 #include "cpu/amd/model_fxx/init_cpus.c"
76 #include "cpu/amd/model_fxx/fidvid.c"
77 #include "northbridge/amd/amdk8/early_ht.c"
79 static void sio_setup(void)
83 device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
85 /* Subject decoding */
86 byte = pci_read_config8(dev, 0x7b);
88 pci_write_config8(dev, 0x7b, byte);
90 /* LPC Positive Decode 0 */
91 dword = pci_read_config32(dev, 0xa0);
92 dword |= (1 << 0); /* COM1 */
93 pci_write_config32(dev, 0xa0, dword);
96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
98 static const u16 spd_addr[] = {
99 DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */
100 DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */
103 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
104 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
106 unsigned bsp_apicid = 0;
108 if (!cpu_init_detectedx && boot_cpu()) {
109 /* Allow the HT devices to be found. */
110 enumerate_ht_chain();
115 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
117 /* FIXME: This should be part of the Super I/O code/config. */
118 pnp_enter_ext_func_mode(SERIAL_DEV);
119 pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */
120 it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
121 pnp_exit_ext_func_mode(SERIAL_DEV);
123 setup_mb_resource_map();
125 report_bist_failure(bist);
127 mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
128 early_usbdebug_init();
132 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
133 printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
135 #if CONFIG_MEM_TRAIN_SEQ == 1
136 /* In BSP so could hold all AP until sysinfo is in RAM. */
137 set_sysinfo_in_ram(0);
140 setup_coherent_ht_domain(); /* Routing table and start other core0. */
141 wait_all_core0_started();
143 #if CONFIG_LOGICAL_CPUS == 1
145 * It is said that we should start core1 after all core0 launched
146 * becase optimize_link_coherent_ht is moved out from
147 * setup_coherent_ht_domain, so here need to make sure last core0 is
148 * started, esp for two way system (there may be APIC ID conflicts in
152 wait_all_other_cores_started(bsp_apicid);
155 /* Set up chains and store link pair for optimization later. */
156 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
160 init_timer(); /* Need to use TMICT to synconize FID/VID. */
162 needs_reset |= optimize_link_coherent_ht();
163 needs_reset |= optimize_link_incoherent_ht(sysinfo);
164 needs_reset |= mcp55_early_setup_x();
167 * FIDVID change will issue one LDTSTOP and the HT change will be
171 print_info("ht reset -\n");
174 allow_all_aps_stop(bsp_apicid);
176 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
180 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
182 /* BSP switch stack to RAM and copy sysinfo RAM now. */