src/mainboard/asus/m2n-e/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #if CONFIG_K8_REV_F_SUPPORT == 1
  24 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  25 #endif
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <device/pci_ids.h>
  31 #include <arch/io.h>
  32 #include <device/pnp_def.h>
  33 #include <arch/romcc_io.h>
  34 #include <cpu/x86/lapic.h>
  35 #include <pc80/mc146818rtc.h>
  36 #include <console/console.h>
  37 #include <cpu/amd/model_fxx_rev.h>
  38 #include "southbridge/nvidia/mcp55/early_smbus.c"
  39 #include "northbridge/amd/amdk8/raminit.h"
  40 #include "cpu/amd/model_fxx/apic_timer.c"
  41 #include "lib/delay.c"
  42 #include <lib.h>
  43 #include <spd.h>
  44 #include "cpu/x86/lapic/boot_cpu.c"
  45 #include "northbridge/amd/amdk8/reset_test.c"
  46 #include "superio/ite/it8716f/early_serial.c"
  47 #include "superio/ite/it8716f/early_init.c"
  48 #include "cpu/x86/bist.h"
  49 #include "northbridge/amd/amdk8/debug.c"
  50 #include "cpu/x86/mtrr/earlymtrr.c"
  51 #include "northbridge/amd/amdk8/setup_resource_map.c"
  52 #include "southbridge/nvidia/mcp55/early_ctrl.c"
  53
  54 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl) {}
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
  58
  59 static inline int spd_read_byte(unsigned int device, unsigned int address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64 #include "northbridge/amd/amdk8/f.h"
  65 #include "northbridge/amd/amdk8/incoherent_ht.c"
  66 #include "northbridge/amd/amdk8/coherent_ht.c"
  67 #include "northbridge/amd/amdk8/raminit_f.c"
  68 #include "lib/generic_sdram.c"
  69 #include "resourcemap.c"
  70 #include "cpu/amd/dualcore/dualcore.c"
  71 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
  72 #include "southbridge/nvidia/mcp55/early_setup_car.c"
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75 #include "cpu/amd/model_fxx/fidvid.c"
  76 #include "northbridge/amd/amdk8/early_ht.c"
  77
  78 static void sio_setup(void)
  79 {
  80         u8 byte;
  81         u32 dword;
  82         device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
  83
  84         /* Subject decoding */
  85         byte = pci_read_config8(dev, 0x7b);
  86         byte |= (1 << 5);
  87         pci_write_config8(dev, 0x7b, byte);
  88
  89         /* LPC Positive Decode 0 */
  90         dword = pci_read_config32(dev, 0xa0);
  91         dword |= (1 << 0); /* COM1 */
  92         pci_write_config32(dev, 0xa0, dword);
  93 }
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const u16 spd_addr[] = {
  98                 DIMM0, DIMM2, 0, 0,     /* Channel A (DIMM_A1, DIMM_A2) */
  99                 DIMM1, DIMM3, 0, 0,     /* Channel B (DIMM_B1, DIMM_B2) */
 100         };
 101
 102         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 103                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 104         int needs_reset = 0;
 105         unsigned bsp_apicid = 0;
 106
 107         if (!cpu_init_detectedx && boot_cpu()) {
 108                 /* Allow the HT devices to be found. */
 109                 enumerate_ht_chain();
 110                 sio_setup();
 111         }
 112
 113         if (bist == 0)
 114                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 115
 116         /* FIXME: This should be part of the Super I/O code/config. */
 117         pnp_enter_ext_func_mode(SERIAL_DEV);
 118         pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */
 119         it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 120         pnp_exit_ext_func_mode(SERIAL_DEV);
 121
 122         setup_mb_resource_map();
 123         report_bist_failure(bist);
 124         console_init();
 125
 126         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
 127         printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
 128
 129 #if CONFIG_MEM_TRAIN_SEQ == 1
 130         /* In BSP so could hold all AP until sysinfo is in RAM. */
 131         set_sysinfo_in_ram(0);
 132 #endif
 133
 134         setup_coherent_ht_domain(); /* Routing table and start other core0. */
 135         wait_all_core0_started();
 136
 137 #if CONFIG_LOGICAL_CPUS == 1
 138         /*
 139          * It is said that we should start core1 after all core0 launched
 140          * becase optimize_link_coherent_ht is moved out from
 141          * setup_coherent_ht_domain, so here need to make sure last core0 is
 142          * started, esp for two way system (there may be APIC ID conflicts in
 143          * that case).
 144          */
 145         start_other_cores();
 146         wait_all_other_cores_started(bsp_apicid);
 147 #endif
 148
 149         /* Set up chains and store link pair for optimization later. */
 150         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 151
 152         /* TODO: FIDVID */
 153
 154         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 155
 156         needs_reset |= optimize_link_coherent_ht();
 157         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 158         needs_reset |= mcp55_early_setup_x();
 159
 160         /*
 161          * FIDVID change will issue one LDTSTOP and the HT change will be
 162          * effective too.
 163          */
 164         if (needs_reset) {
 165                 print_info("ht reset -\n");
 166                 soft_reset();
 167         }
 168         allow_all_aps_stop(bsp_apicid);
 169
 170         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 171
 172         enable_smbus();
 173
 174         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 175
 176         /* BSP switch stack to RAM and copy sysinfo RAM now. */
 177         post_cache_as_ram();
 178 }