src/mainboard/asus/a8v-e_se/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 unsigned int get_sbdn(unsigned bus);
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "northbridge/amd/amdk8/early_ht.c"
  43 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  44 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
  45 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49 #include <spd.h>
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  52 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
  53 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
  54
  55 static void memreset(int controllers, const struct mem_controller *ctrl)
  56 {
  57 }
  58
  59 static inline int spd_read_byte(unsigned device, unsigned address)
  60 {
  61         return smbus_read_byte(device, address);
  62 }
  63
  64 static void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66 }
  67
  68 #include <reset.h>
  69 void soft_reset(void)
  70 {
  71         uint8_t tmp;
  72
  73         set_bios_reset();
  74         print_debug("soft reset \n");
  75
  76         /* PCI reset */
  77         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
  78         tmp |= 0x01;
  79         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
  80
  81         while (1) {
  82                 /* daisy daisy ... */
  83                 hlt();
  84         }
  85 }
  86
  87 // defines S3_NVRAM_EARLY:
  88 #include "southbridge/via/k8t890/k8t890_early_car.c"
  89
  90 #include "northbridge/amd/amdk8/amdk8.h"
  91 #include "northbridge/amd/amdk8/incoherent_ht.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "northbridge/amd/amdk8/raminit.c"
  94 #include "lib/generic_sdram.c"
  95
  96 #include "cpu/amd/dualcore/dualcore.c"
  97
  98 #include "cpu/amd/car/post_cache_as_ram.c"
  99 #include "cpu/amd/model_fxx/init_cpus.c"
 100 #include "cpu/amd/model_fxx/fidvid.c"
 101 #include "northbridge/amd/amdk8/resourcemap.c"
 102
 103 unsigned int get_sbdn(unsigned bus)
 104 {
 105         device_t dev;
 106
 107         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 108                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
 109         return (dev >> 15) & 0x1f;
 110 }
 111
 112 static void sio_init(void)
 113 {
 114         u8 reg;
 115
 116         pnp_enter_ext_func_mode(SERIAL_DEV);
 117         /* We have 24MHz input. */
 118         reg = pnp_read_config(SERIAL_DEV, 0x24);
 119         pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
 120         /* We have GPIO for KB/MS pin. */
 121         reg = pnp_read_config(SERIAL_DEV, 0x2a);
 122         pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
 123         /* We have all RESTOUT and even some reserved bits, too. */
 124         reg = pnp_read_config(SERIAL_DEV, 0x2c);
 125         pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
 126         pnp_exit_ext_func_mode(SERIAL_DEV);
 127
 128         pnp_enter_ext_func_mode(ACPI_DEV);
 129         pnp_set_logical_device(ACPI_DEV);
 130         /*
 131          * Set the delay rising time from PWROK_LP to PWROK_ST to
 132          * 300 - 600ms, and 0 to vice versa.
 133          */
 134         reg = pnp_read_config(ACPI_DEV, 0xe6);
 135         pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
 136         /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
 137         reg = pnp_read_config(ACPI_DEV, 0xe4);
 138         pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
 139         pnp_exit_ext_func_mode(ACPI_DEV);
 140
 141         pnp_enter_ext_func_mode(GPIO_DEV);
 142         pnp_set_logical_device(GPIO_DEV);
 143         /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
 144         pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
 145         pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
 146         pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
 147         pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
 148         pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
 149         pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
 150         pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
 151         pnp_exit_ext_func_mode(GPIO_DEV);
 152 }
 153
 154 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 155 {
 156         static const uint16_t spd_addr[] = {
 157                 // Node 0
 158                 DIMM0, DIMM2, 0, 0,
 159                 DIMM1, DIMM3, 0, 0,
 160                 // Node 1
 161                 DIMM4, DIMM6, 0, 0,
 162                 DIMM5, DIMM7, 0, 0,
 163         };
 164         unsigned bsp_apicid = 0;
 165         int needs_reset = 0;
 166         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 167                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 168
 169         sio_init();
 170         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 171         uart_init();
 172         console_init();
 173         enable_rom_decode();
 174
 175         print_info("now booting... fallback\n");
 176
 177         /* Is this a CPU only reset? Or is this a secondary CPU? */
 178         if (!cpu_init_detectedx && boot_cpu()) {
 179                 /* Nothing special needs to be done to find bus 0. */
 180                 /* Allow the HT devices to be found. */
 181                 enumerate_ht_chain();
 182         }
 183
 184         sio_init();
 185         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 186         uart_init();
 187         console_init();
 188         enable_rom_decode();
 189
 190         print_info("now booting... real_main\n");
 191
 192         if (bist == 0)
 193                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 194
 195         /* Halt if there was a built in self test failure. */
 196         report_bist_failure(bist);
 197
 198         setup_default_resource_map();
 199         setup_coherent_ht_domain();
 200         wait_all_core0_started();
 201
 202         print_info("now booting... Core0 started\n");
 203
 204 #if CONFIG_LOGICAL_CPUS==1
 205         /* It is said that we should start core1 after all core0 launched. */
 206         start_other_cores();
 207         wait_all_other_cores_started(bsp_apicid);
 208 #endif
 209         init_timer();
 210         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 211
 212         needs_reset = optimize_link_coherent_ht();
 213         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 214         needs_reset |= k8t890_early_setup_ht();
 215
 216         if (needs_reset) {
 217                 print_debug("ht reset -\n");
 218                 soft_reset();
 219         }
 220
 221         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 222         enable_fid_change();
 223         init_fidvid_bsp(bsp_apicid);
 224
 225         /* Stop the APs so we can start them later in init. */
 226         allow_all_aps_stop(bsp_apicid);
 227
 228         /* It's the time to set ctrl now. */
 229         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 230
 231         enable_smbus();
 232         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 233         post_cache_as_ram();
 234 }
 235