2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 unsigned int get_sbdn(unsigned bus);
29 #include <device/pci_def.h>
31 #include <device/pnp_def.h>
32 #include <arch/romcc_io.h>
33 #include <cpu/x86/lapic.h>
34 #include <pc80/mc146818rtc.h>
35 #include <console/console.h>
36 #include <cpu/amd/model_fxx_rev.h>
37 #include "northbridge/amd/amdk8/raminit.h"
38 #include "cpu/amd/model_fxx/apic_timer.c"
39 #include "lib/delay.c"
40 #include "cpu/x86/lapic/boot_cpu.c"
41 #include "northbridge/amd/amdk8/reset_test.c"
42 #include "northbridge/amd/amdk8/early_ht.c"
43 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
44 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
45 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
46 #include "cpu/x86/mtrr/earlymtrr.c"
47 #include "cpu/x86/bist.h"
48 #include "northbridge/amd/amdk8/setup_resource_map.c"
50 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
51 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
52 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
54 static void memreset(int controllers, const struct mem_controller *ctrl)
58 static inline int spd_read_byte(unsigned device, unsigned address)
60 return smbus_read_byte(device, address);
63 static void activate_spd_rom(const struct mem_controller *ctrl)
73 print_debug("soft reset \n");
76 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
78 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
86 // defines S3_NVRAM_EARLY:
87 #include "southbridge/via/k8t890/k8t890_early_car.c"
89 #include "northbridge/amd/amdk8/amdk8.h"
90 #include "northbridge/amd/amdk8/incoherent_ht.c"
91 #include "northbridge/amd/amdk8/coherent_ht.c"
92 #include "northbridge/amd/amdk8/raminit.c"
93 #include "lib/generic_sdram.c"
95 #include "cpu/amd/dualcore/dualcore.c"
97 #include "cpu/amd/car/post_cache_as_ram.c"
98 #include "cpu/amd/model_fxx/init_cpus.c"
99 #include "cpu/amd/model_fxx/fidvid.c"
100 #include "northbridge/amd/amdk8/resourcemap.c"
102 unsigned int get_sbdn(unsigned bus)
106 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
107 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
108 return (dev >> 15) & 0x1f;
111 static void sio_init(void)
115 pnp_enter_ext_func_mode(SERIAL_DEV);
116 /* We have 24MHz input. */
117 reg = pnp_read_config(SERIAL_DEV, 0x24);
118 pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
119 /* We have GPIO for KB/MS pin. */
120 reg = pnp_read_config(SERIAL_DEV, 0x2a);
121 pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
122 /* We have all RESTOUT and even some reserved bits, too. */
123 reg = pnp_read_config(SERIAL_DEV, 0x2c);
124 pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
125 pnp_exit_ext_func_mode(SERIAL_DEV);
127 pnp_enter_ext_func_mode(ACPI_DEV);
128 pnp_set_logical_device(ACPI_DEV);
130 * Set the delay rising time from PWROK_LP to PWROK_ST to
131 * 300 - 600ms, and 0 to vice versa.
133 reg = pnp_read_config(ACPI_DEV, 0xe6);
134 pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
135 /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
136 reg = pnp_read_config(ACPI_DEV, 0xe4);
137 pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
138 pnp_exit_ext_func_mode(ACPI_DEV);
140 pnp_enter_ext_func_mode(GPIO_DEV);
141 pnp_set_logical_device(GPIO_DEV);
142 /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
143 pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
144 pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
145 pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
146 pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
147 pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
148 pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
149 pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
150 pnp_exit_ext_func_mode(GPIO_DEV);
153 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
155 static const uint16_t spd_addr[] = {
157 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
158 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
160 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
161 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
163 unsigned bsp_apicid = 0;
165 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
166 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
169 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
174 print_info("now booting... fallback\n");
176 /* Is this a CPU only reset? Or is this a secondary CPU? */
177 if (!cpu_init_detectedx && boot_cpu()) {
178 /* Nothing special needs to be done to find bus 0. */
179 /* Allow the HT devices to be found. */
180 enumerate_ht_chain();
184 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
189 print_info("now booting... real_main\n");
192 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
194 /* Halt if there was a built in self test failure. */
195 report_bist_failure(bist);
197 setup_default_resource_map();
198 setup_coherent_ht_domain();
199 wait_all_core0_started();
201 print_info("now booting... Core0 started\n");
203 #if CONFIG_LOGICAL_CPUS==1
204 /* It is said that we should start core1 after all core0 launched. */
206 wait_all_other_cores_started(bsp_apicid);
209 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
211 needs_reset = optimize_link_coherent_ht();
212 needs_reset |= optimize_link_incoherent_ht(sysinfo);
213 needs_reset |= k8t890_early_setup_ht();
216 print_debug("ht reset -\n");
220 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
222 init_fidvid_bsp(bsp_apicid);
224 /* Stop the APs so we can start them later in init. */
225 allow_all_aps_stop(bsp_apicid);
227 /* It's the time to set ctrl now. */
228 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
231 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);