2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 unsigned int get_sbdn(unsigned bus);
27 /* Used by init_cpus and fidvid */
30 /* If we want to wait for core1 done before DQS training, set it to 0. */
31 #define SET_FIDVID_CORE0_ONLY 1
35 #include <device/pci_def.h>
37 #include <device/pnp_def.h>
38 #include <arch/romcc_io.h>
39 #include <cpu/x86/lapic.h>
40 #include <pc80/mc146818rtc.h>
41 #include <console/console.h>
42 #include <cpu/amd/model_fxx_rev.h>
43 #include "northbridge/amd/amdk8/raminit.h"
44 #include "cpu/amd/model_fxx/apic_timer.c"
45 #include "lib/delay.c"
46 #include "cpu/x86/lapic/boot_cpu.c"
47 #include "northbridge/amd/amdk8/reset_test.c"
48 #include "northbridge/amd/amdk8/early_ht.c"
49 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
50 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
51 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
52 #include "cpu/x86/mtrr/earlymtrr.c"
53 #include "cpu/x86/bist.h"
54 #include "northbridge/amd/amdk8/setup_resource_map.c"
56 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
57 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
58 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
59 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
61 static void memreset(int controllers, const struct mem_controller *ctrl)
65 static inline int spd_read_byte(unsigned device, unsigned address)
67 return smbus_read_byte(device, address);
70 static void activate_spd_rom(const struct mem_controller *ctrl)
80 print_debug("soft reset \n");
83 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
85 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
93 // defines S3_NVRAM_EARLY:
94 #include "southbridge/via/k8t890/k8t890_early_car.c"
96 #include "northbridge/amd/amdk8/amdk8.h"
97 #include "northbridge/amd/amdk8/incoherent_ht.c"
98 #include "northbridge/amd/amdk8/coherent_ht.c"
99 #include "northbridge/amd/amdk8/raminit.c"
100 #include "lib/generic_sdram.c"
102 #include "cpu/amd/dualcore/dualcore.c"
104 #include "cpu/amd/car/post_cache_as_ram.c"
105 #include "cpu/amd/model_fxx/init_cpus.c"
106 #include "cpu/amd/model_fxx/fidvid.c"
107 #include "northbridge/amd/amdk8/resourcemap.c"
109 unsigned int get_sbdn(unsigned bus)
113 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
114 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
115 return (dev >> 15) & 0x1f;
118 static void sio_init(void)
122 pnp_enter_ext_func_mode(SERIAL_DEV);
123 /* We have 24MHz input. */
124 reg = pnp_read_config(SERIAL_DEV, 0x24);
125 pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
126 /* We have GPIO for KB/MS pin. */
127 reg = pnp_read_config(SERIAL_DEV, 0x2a);
128 pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
129 /* We have all RESTOUT and even some reserved bits, too. */
130 reg = pnp_read_config(SERIAL_DEV, 0x2c);
131 pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
132 pnp_exit_ext_func_mode(SERIAL_DEV);
134 pnp_enter_ext_func_mode(ACPI_DEV);
135 pnp_set_logical_device(ACPI_DEV);
137 * Set the delay rising time from PWROK_LP to PWROK_ST to
138 * 300 - 600ms, and 0 to vice versa.
140 reg = pnp_read_config(ACPI_DEV, 0xe6);
141 pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
142 /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
143 reg = pnp_read_config(ACPI_DEV, 0xe4);
144 pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
145 pnp_exit_ext_func_mode(ACPI_DEV);
147 pnp_enter_ext_func_mode(GPIO_DEV);
148 pnp_set_logical_device(GPIO_DEV);
149 /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
150 pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
151 pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
152 pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
153 pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
154 pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
155 pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
156 pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
157 pnp_exit_ext_func_mode(GPIO_DEV);
160 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
162 static const uint16_t spd_addr[] = {
164 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
165 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
167 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
168 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
170 unsigned bsp_apicid = 0;
172 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
173 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
176 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
181 print_info("now booting... fallback\n");
183 /* Is this a CPU only reset? Or is this a secondary CPU? */
184 if (!cpu_init_detectedx && boot_cpu()) {
185 /* Nothing special needs to be done to find bus 0. */
186 /* Allow the HT devices to be found. */
187 enumerate_ht_chain();
191 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
196 print_info("now booting... real_main\n");
199 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
201 /* Halt if there was a built in self test failure. */
202 report_bist_failure(bist);
204 setup_default_resource_map();
205 setup_coherent_ht_domain();
206 wait_all_core0_started();
208 print_info("now booting... Core0 started\n");
210 #if CONFIG_LOGICAL_CPUS==1
211 /* It is said that we should start core1 after all core0 launched. */
213 wait_all_other_cores_started(bsp_apicid);
216 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
218 needs_reset = optimize_link_coherent_ht();
219 needs_reset |= optimize_link_incoherent_ht(sysinfo);
220 needs_reset |= k8t890_early_setup_ht();
223 print_debug("ht reset -\n");
227 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
229 init_fidvid_bsp(bsp_apicid);
231 /* Stop the APs so we can start them later in init. */
232 allow_all_aps_stop(bsp_apicid);
234 /* It's the time to set ctrl now. */
235 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
238 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);