2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 include /config/nofailovercalculation.lb
24 default CONFIG_ROM_PAYLOAD = 1
33 depends "$(MAINBOARD)/dsdt.asl"
34 action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
35 action "mv dsdt.hex dsdt.c"
39 if HAVE_MP_TABLE object mptable.o end
40 if HAVE_PIRQ_TABLE object irq_tables.o end
44 makerule ./cache_as_ram_auto.o
45 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
46 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
49 makerule ./cache_as_ram_auto.inc
50 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
51 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
52 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
53 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
58 mainboardinit cpu/x86/16bit/entry16.inc
59 ldscript /cpu/x86/16bit/entry16.lds
60 mainboardinit southbridge/via/k8t890/romstrap.inc
61 ldscript /southbridge/via/k8t890/romstrap.lds
64 mainboardinit cpu/x86/32bit/entry32.inc
67 ldscript /cpu/x86/32bit/entry32.lds
70 ldscript /cpu/amd/car/cache_as_ram.lds
74 mainboardinit cpu/x86/16bit/reset16.inc
75 ldscript /cpu/x86/16bit/reset16.lds
77 mainboardinit cpu/x86/32bit/reset32.inc
78 ldscript /cpu/x86/32bit/reset32.lds
81 mainboardinit cpu/amd/car/cache_as_ram.inc
84 ldscript /arch/i386/lib/failover.lds
88 initobject cache_as_ram_auto.o
90 mainboardinit ./cache_as_ram_auto.inc
95 chip northbridge/amd/amdk8/root_complex # Root complex
96 device apic_cluster 0 on # APIC cluster
97 chip cpu/amd/socket_939 # CPU
98 device apic 0 on end # APIC
101 device pci_domain 0 on # PCI domain
102 chip northbridge/amd/amdk8 # mc0
103 device pci 18.0 on # Northbridge
104 # Devices on link 0, link 0 == LDT 0
105 chip southbridge/via/vt8237r # Southbridge
106 register "ide0_enable" = "1" # Enable IDE channel 0
107 register "ide1_enable" = "1" # Enable IDE channel 1
108 register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
109 register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
110 register "fn_ctrl_lo" = "0" # Enable SB functions
111 register "fn_ctrl_hi" = "0xad" # Enable SB functions
112 device pci 0.0 on end # HT
113 device pci f.1 on end # IDE
114 device pci 11.0 on # LPC
115 chip drivers/generic/generic # DIMM 0-0-0
118 chip drivers/generic/generic # DIMM 0-0-1
121 chip drivers/generic/generic # DIMM 0-1-0
124 chip drivers/generic/generic # DIMM 0-1-1
127 chip superio/winbond/w83627ehg # Super I/O
128 device pnp 2e.0 on # Floppy
133 device pnp 2e.1 on # Parallel port
138 device pnp 2e.2 on # Com1
142 device pnp 2e.3 off # Com2 (N/A on this board)
146 device pnp 2e.5 off # PS/2 keyboard (off)
148 device pnp 2e.106 off # Serial flash
151 device pnp 2e.007 off # GPIO 1
153 device pnp 2e.107 on # Game port
156 device pnp 2e.207 on # MIDI
160 device pnp 2e.307 off # GPIO 6
162 device pnp 2e.8 off # WDTO_PLED
164 device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
166 device pnp 2e.109 off # GPIO 3
168 device pnp 2e.209 off # GPIO 4
170 device pnp 2e.309 on # GPIO5
172 device pnp 2e.a off # ACPI
174 device pnp 2e.b on # Hardware monitor
180 device pci 12.0 off end # VIA LAN (off, other chip used)
182 chip southbridge/via/k8t890 # "Southbridge" K8T890
185 device pci 18.1 on end
186 device pci 18.2 on end
187 device pci 18.3 on end