src/mainboard/asus/a8v-e_se/Config.lb

   1 ##
   2 ## This file is part of the LinuxBIOS project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ##
  25 ## Compute the location and size of where this firmware image
  26 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  27 ##
  28     if USE_FALLBACK_IMAGE
  29         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  30         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
  31     else
  32         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  33         default ROM_SECTION_OFFSET = 0
  34     end
  35
  36 ##
  37 ## Compute the start location and size size of
  38 ## The linuxBIOS bootloader.
  39 ##
  40 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  41 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  42 default CONFIG_ROM_PAYLOAD     = 1
  43
  44 ##
  45 ## Compute where this copy of linuxBIOS will start in the boot rom
  46 ##
  47 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  48
  49 ##
  50 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  51 ## execution speed.
  52 ##
  53 ## XIP_ROM_SIZE must be a power of 2.
  54 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  55 ##
  56 default XIP_ROM_SIZE=65536
  57 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  58
  59 arch i386 end
  60
  61 ##
  62 ## Build the objects we have code for in this directory.
  63 ##
  64
  65 driver mainboard.o
  66
  67 if HAVE_ACPI_TABLES
  68         object acpi_tables.o
  69         object fadt.o
  70         makerule dsdt.c
  71                 depends "$(MAINBOARD)/dsdt.asl"
  72                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
  73                 action  "mv dsdt.hex dsdt.c"
  74         end
  75         object ./dsdt.o
  76 end
  77
  78 if HAVE_MP_TABLE object mptable.o end
  79 if HAVE_PIRQ_TABLE object irq_tables.o end
  80 #object reset.o
  81 if USE_DCACHE_RAM
  82
  83         if CONFIG_USE_INIT
  84                 makerule ./cache_as_ram_auto.o
  85                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  86                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  87                 end
  88         else
  89                 makerule ./cache_as_ram_auto.inc
  90                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  91                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  92                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  93                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  94                 end
  95         end
  96
  97 end
  98
  99 ##
 100 ## Build our 16 bit and 32 bit linuxBIOS entry code
 101 ##
 102
 103 if USE_FALLBACK_IMAGE
 104         mainboardinit cpu/x86/16bit/entry16.inc
 105         ldscript /cpu/x86/16bit/entry16.lds
 106         mainboardinit southbridge/via/k8t890/romstrap.inc
 107         ldscript /southbridge/via/k8t890/romstrap.lds
 108
 109 end
 110
 111 mainboardinit cpu/x86/32bit/entry32.inc
 112
 113 if USE_DCACHE_RAM
 114         if CONFIG_USE_INIT
 115                 ldscript /cpu/x86/32bit/entry32.lds
 116         end
 117
 118         if CONFIG_USE_INIT
 119                 ldscript /cpu/amd/car/cache_as_ram.lds
 120         end
 121 end
 122
 123
 124 ##
 125 ## Build our reset vector (This is where linuxBIOS is entered)
 126 ##
 127
 128 if USE_FALLBACK_IMAGE
 129         mainboardinit cpu/x86/16bit/reset16.inc
 130         ldscript /cpu/x86/16bit/reset16.lds
 131 else
 132         mainboardinit cpu/x86/32bit/reset32.inc
 133         ldscript /cpu/x86/32bit/reset32.lds
 134 end
 135
 136 if USE_DCACHE_RAM
 137         ##
 138         ## Setup Cache-As-Ram
 139         ##
 140         mainboardinit cpu/amd/car/cache_as_ram.inc
 141 end
 142
 143 ###
 144 ### This is the early phase of linuxBIOS startup
 145 ### Things are delicate and we test to see if we should
 146 ### failover to another image.
 147 ###
 148
 149 if USE_FALLBACK_IMAGE
 150         if USE_DCACHE_RAM
 151                 ldscript /arch/i386/lib/failover.lds
 152         end
 153 end
 154
 155
 156 ##
 157 ## Setup RAM
 158 ##
 159 if USE_DCACHE_RAM
 160
 161         if CONFIG_USE_INIT
 162                 initobject cache_as_ram_auto.o
 163         else
 164                 mainboardinit ./cache_as_ram_auto.inc
 165         end
 166 end
 167
 168 ##
 169 ## Include the secondary Configuration files
 170 ##
 171 if CONFIG_CHIP_NAME
 172         config chip.h
 173 end
 174
 175 chip northbridge/amd/amdk8/root_complex
 176         device apic_cluster 0 on
 177                 chip cpu/amd/socket_939
 178                         device apic 0 on end
 179                 end
 180         end
 181
 182        device pci_domain 0 on
 183                chip northbridge/amd/amdk8 #mc0
 184                        device pci 18.0 on #  northbridge
 185                                #  devices on link 0, link 0 == LDT 0
 186                                chip southbridge/via/vt8237r
 187                                         #both IDE channels
 188                                         register "ide0_enable" = "1"
 189                                         register "ide1_enable" = "1"
 190                                         #both cables are 80pin
 191                                         register "ide0_80pin_cable" = "1"
 192                                         register "ide1_80pin_cable" = "1"
 193                                         #enables the functions of SB
 194                                         register "fn_ctrl_lo" = "0"
 195                                         register "fn_ctrl_hi" = "0xad"
 196
 197                                        device pci 0.0 on end   # HT
 198                                        device pci f.1 on end   # IDE
 199                                        device pci 11.0 on # LPC
 200                                                 chip drivers/generic/generic #dimm 0-0-0
 201                                                         device i2c 50 on end
 202                                                 end
 203                                                 chip drivers/generic/generic #dimm 0-0-1
 204                                                         device i2c 51 on end
 205                                                 end
 206                                                 chip drivers/generic/generic #dimm 0-1-0
 207                                                         device i2c 52 on end
 208                                                 end
 209                                                 chip drivers/generic/generic #dimm 0-1-1
 210                                                         device i2c 53 on end
 211                                                 end
 212
 213                                                chip superio/winbond/w83627ehg
 214                                                        device pnp 2e.0 on #  Floppy
 215                                                                io 0x60 = 0x3f0
 216                                                                irq 0x70 = 6
 217                                                                drq 0x74 = 2
 218                                                        end
 219                                                        device pnp 2e.1 on #  Parallel Port
 220                                                                io 0x60 = 0x378
 221                                                                irq 0x70 = 7
 222                                                                drq 0x74 = 3
 223                                                        end
 224                                                        device pnp 2e.2 on #  Com1
 225                                                                io 0x60 = 0x3f8
 226                                                                irq 0x70 = 4
 227                                                        end
 228                                                        device pnp 2e.3 off #  Com2
 229                                                                io 0x60 = 0x2f8
 230                                                                irq 0x70 = 3
 231                                                        end
 232                                                        device pnp 2e.5 off #keyb OFF
 233                                                        end
 234                                                        device pnp 2e.6 off #  SERIAL_FLASH
 235                                                                io 0x60 = 0x100
 236                                                        end
 237                                                        device pnp 2e.7 off #  GAME_MIDI_GIPO1
 238                                                               # io 0x60 = 0x220
 239                                                               # io 0x62 = 0x300
 240                                                               # irq 0x70 = a
 241                                                        end
 242                                                        device pnp 2e.8 off end #  WDTO_PLED
 243                                                        device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9
 244                                                                                 #GPIO 5 and 2 active
 245                                                                 #0xe0 = de
 246                                                                 #0xe1 = 01
 247                                                                 #0xe2 = 00
 248                                                                 #0xe3 = 03
 249                                                                 #0xe4 = a4
 250                                                                 #0xe5 = 00
 251
 252                                                        device pnp 2e.a off end #  ACPI
 253                                                        device pnp 2e.b on #  HW Monitor
 254                                                                io 0x60 = 0x290
 255                                                                irq 0x70 = 0
 256                                                        end
 257                                                end #end SIO
 258                                        end #end 11
 259
 260                                        device pci 12.0 off end # VIA LAN is disabled, Asus used other chip
 261                                end
 262
 263                                chip southbridge/via/k8t890
 264                                 end
 265
 266                        end #  device pci 18.0
 267                        device pci 18.1 on end
 268                        device pci 18.2 on end
 269                        device pci 18.3 on end
 270                end #mc0
 271
 272        end # pci_domain
 273
 274 end # root_complex