src/mainboard/asus/a8n_e/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 /* Used by it8712f_enable_serial(). */
  25 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include "cpu/x86/lapic/boot_cpu.c"
  36 #include "northbridge/amd/amdk8/reset_test.c"
  37 #include "superio/ite/it8712f/it8712f_early_serial.c"
  38 #include <cpu/amd/model_fxx_rev.h>
  39 #include <console/console.h>
  40 #include "northbridge/amd/amdk8/incoherent_ht.c"
  41 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include "northbridge/amd/amdk8/debug.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49 #include "northbridge/amd/amdk8/coherent_ht.c"
  50 #include "cpu/amd/dualcore/dualcore.c"
  51 #include <spd.h>
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55         /* Nothing to do. */
  56 }
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60         /* Nothing to do. */
  61 }
  62
  63 static inline int spd_read_byte(unsigned device, unsigned address)
  64 {
  65         return smbus_read_byte(device, address);
  66 }
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "lib/generic_sdram.c"
  70 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  71 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  72 #include "cpu/amd/car/post_cache_as_ram.c"
  73 #include "cpu/amd/model_fxx/init_cpus.c"
  74 #include "northbridge/amd/amdk8/early_ht.c"
  75
  76 static void sio_setup(void)
  77 {
  78         uint32_t dword;
  79         uint8_t byte;
  80
  81         /* Subject decoding */
  82         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
  83         byte |= 0x20;
  84         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
  85
  86         /* LPC Positive Decode 0 */
  87         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
  88         dword |= (1 << 0) | (1 << 1);   /* Serial 0, Serial 1 */
  89         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
  90 }
  91
  92 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  93 {
  94         static const uint16_t spd_addr[] = {
  95                 DIMM0, DIMM2, 0, 0,
  96                 DIMM1, DIMM3, 0, 0,
  97 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  98                 DIMM4, DIMM6, 0, 0,
  99                 DIMM5, DIMM7, 0, 0,
 100 #endif
 101         };
 102
 103         int needs_reset;
 104         unsigned nodes, bsp_apicid = 0;
 105         struct mem_controller ctrl[8];
 106
 107         if (!cpu_init_detectedx && boot_cpu()) {
 108                 /* Nothing special needs to be done to find bus 0 */
 109                 /* Allow the HT devices to be found */
 110                 enumerate_ht_chain();
 111
 112                 sio_setup();
 113         }
 114
 115         if (bist == 0)
 116                 bsp_apicid = init_cpus(cpu_init_detectedx);
 117
 118         it8712f_24mhz_clkin();
 119         it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 120         uart_init();
 121         console_init();
 122
 123         /* Halt if there was a built in self test failure */
 124         report_bist_failure(bist);
 125
 126 #if 0
 127         dump_pci_device(PCI_DEV(0, 0x18, 0));
 128 #endif
 129
 130         needs_reset = setup_coherent_ht_domain();
 131
 132         wait_all_core0_started();
 133 #if CONFIG_LOGICAL_CPUS==1
 134         /* It is said that we should start core1 after all core0 launched. */
 135         start_other_cores();
 136         wait_all_other_cores_started(bsp_apicid);
 137 #endif
 138
 139         needs_reset |= ht_setup_chains_x();
 140         needs_reset |= ck804_early_setup_x();
 141
 142         if (needs_reset) {
 143                 print_info("ht reset -\n");
 144                 soft_reset();
 145         }
 146
 147         allow_all_aps_stop(bsp_apicid);
 148
 149         nodes = get_nodes();
 150         /* It's the time to set ctrl now. */
 151         fill_mem_ctrl(nodes, ctrl, spd_addr);
 152
 153         enable_smbus();
 154
 155 #if 0
 156         dump_spd_registers(&ctrl[0]);
 157         dump_smbus_registers();
 158 #endif
 159
 160         sdram_initialize(nodes, ctrl);
 161
 162 #if 0
 163         print_pci_devices();
 164         dump_pci_devices();
 165 #endif
 166
 167         post_cache_as_ram();
 168 }