2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /* Used by it8712f_enable_serial(). */
25 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
27 /* Used by raminit. */
29 #if CONFIG_LOGICAL_CPUS == 1
30 #define SET_NB_CFG_54 1
35 #include <device/pci_def.h>
37 #include <device/pnp_def.h>
38 #include <arch/romcc_io.h>
39 #include <cpu/x86/lapic.h>
40 #include <pc80/mc146818rtc.h>
41 #include "cpu/x86/lapic/boot_cpu.c"
42 #include "northbridge/amd/amdk8/reset_test.c"
43 #include "superio/ite/it8712f/it8712f_early_serial.c"
44 #include <cpu/amd/model_fxx_rev.h>
45 #include <console/console.h>
46 #include "northbridge/amd/amdk8/incoherent_ht.c"
47 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
48 #include "northbridge/amd/amdk8/raminit.h"
49 #include "cpu/amd/model_fxx/apic_timer.c"
50 #include "lib/delay.c"
51 #include "northbridge/amd/amdk8/debug.c"
52 #include "cpu/x86/mtrr/earlymtrr.c"
53 #include "cpu/x86/bist.h"
54 #include "northbridge/amd/amdk8/setup_resource_map.c"
55 #include "northbridge/amd/amdk8/coherent_ht.c"
56 #include "cpu/amd/dualcore/dualcore.c"
58 static void memreset(int controllers, const struct mem_controller *ctrl)
63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
68 static inline int spd_read_byte(unsigned device, unsigned address)
70 return smbus_read_byte(device, address);
73 #include "northbridge/amd/amdk8/raminit.c"
74 #include "lib/generic_sdram.c"
75 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
76 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
78 #include "cpu/amd/car/post_cache_as_ram.c"
79 #include "cpu/amd/model_fxx/init_cpus.c"
81 #include "northbridge/amd/amdk8/early_ht.c"
83 static void sio_setup(void)
88 /* Subject decoding */
89 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
91 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
93 /* LPC Positive Decode 0 */
94 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
95 dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
96 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
101 static const uint16_t spd_addr[] = {
102 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
103 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
104 #if CONFIG_MAX_PHYSICAL_CPUS > 1
105 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
106 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
111 unsigned nodes, bsp_apicid = 0;
112 struct mem_controller ctrl[8];
114 if (!cpu_init_detectedx && boot_cpu()) {
115 /* Nothing special needs to be done to find bus 0 */
116 /* Allow the HT devices to be found */
117 enumerate_ht_chain();
123 bsp_apicid = init_cpus(cpu_init_detectedx);
125 it8712f_24mhz_clkin();
126 it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
130 /* Halt if there was a built in self test failure */
131 report_bist_failure(bist);
134 dump_pci_device(PCI_DEV(0, 0x18, 0));
137 needs_reset = setup_coherent_ht_domain();
139 wait_all_core0_started();
140 #if CONFIG_LOGICAL_CPUS==1
141 /* It is said that we should start core1 after all core0 launched. */
143 wait_all_other_cores_started(bsp_apicid);
146 needs_reset |= ht_setup_chains_x();
147 needs_reset |= ck804_early_setup_x();
150 print_info("ht reset -\n");
154 allow_all_aps_stop(bsp_apicid);
157 /* It's the time to set ctrl now. */
158 fill_mem_ctrl(nodes, ctrl, spd_addr);
163 dump_spd_registers(&ctrl[0]);
164 dump_smbus_registers();
167 sdram_initialize(nodes, ctrl);