src/mainboard/asus/a8n_e/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 /* Used by it8712f_enable_serial(). */
  25 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include "cpu/x86/lapic/boot_cpu.c"
  36 #include "northbridge/amd/amdk8/reset_test.c"
  37 #include "superio/ite/it8712f/it8712f_early_serial.c"
  38 #include <cpu/amd/model_fxx_rev.h>
  39 #include <console/console.h>
  40 #include "northbridge/amd/amdk8/incoherent_ht.c"
  41 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include "northbridge/amd/amdk8/debug.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49 #include "northbridge/amd/amdk8/coherent_ht.c"
  50 #include "cpu/amd/dualcore/dualcore.c"
  51 #include <spd.h>
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55         /* Nothing to do. */
  56 }
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60         /* Nothing to do. */
  61 }
  62
  63 static inline int spd_read_byte(unsigned device, unsigned address)
  64 {
  65         return smbus_read_byte(device, address);
  66 }
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "lib/generic_sdram.c"
  70 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  71 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  72
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75
  76 #include "northbridge/amd/amdk8/early_ht.c"
  77
  78 static void sio_setup(void)
  79 {
  80         uint32_t dword;
  81         uint8_t byte;
  82
  83         /* Subject decoding */
  84         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
  85         byte |= 0x20;
  86         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
  87
  88         /* LPC Positive Decode 0 */
  89         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
  90         dword |= (1 << 0) | (1 << 1);   /* Serial 0, Serial 1 */
  91         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
  92 }
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const uint16_t spd_addr[] = {
  97                 DIMM0, DIMM2, 0, 0,
  98                 DIMM1, DIMM3, 0, 0,
  99 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 100                 DIMM4, DIMM6, 0, 0,
 101                 DIMM5, DIMM7, 0, 0,
 102 #endif
 103         };
 104
 105         int needs_reset;
 106         unsigned nodes, bsp_apicid = 0;
 107         struct mem_controller ctrl[8];
 108
 109         if (!cpu_init_detectedx && boot_cpu()) {
 110                 /* Nothing special needs to be done to find bus 0 */
 111                 /* Allow the HT devices to be found */
 112                 enumerate_ht_chain();
 113
 114                 sio_setup();
 115         }
 116
 117         if (bist == 0)
 118                 bsp_apicid = init_cpus(cpu_init_detectedx);
 119
 120         it8712f_24mhz_clkin();
 121         it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 122         uart_init();
 123         console_init();
 124
 125         /* Halt if there was a built in self test failure */
 126         report_bist_failure(bist);
 127
 128 #if 0
 129         dump_pci_device(PCI_DEV(0, 0x18, 0));
 130 #endif
 131
 132         needs_reset = setup_coherent_ht_domain();
 133
 134         wait_all_core0_started();
 135 #if CONFIG_LOGICAL_CPUS==1
 136         /* It is said that we should start core1 after all core0 launched. */
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140
 141         needs_reset |= ht_setup_chains_x();
 142         needs_reset |= ck804_early_setup_x();
 143
 144         if (needs_reset) {
 145                 print_info("ht reset -\n");
 146                 soft_reset();
 147         }
 148
 149         allow_all_aps_stop(bsp_apicid);
 150
 151         nodes = get_nodes();
 152         /* It's the time to set ctrl now. */
 153         fill_mem_ctrl(nodes, ctrl, spd_addr);
 154
 155         enable_smbus();
 156
 157 #if 0
 158         dump_spd_registers(&ctrl[0]);
 159         dump_smbus_registers();
 160 #endif
 161
 162         sdram_initialize(nodes, ctrl);
 163
 164 #if 0
 165         print_pci_devices();
 166         dump_pci_devices();
 167 #endif
 168
 169         post_cache_as_ram();
 170 }
 171