2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_isa;
32 extern unsigned char bus_ck804[6];
33 extern unsigned apicid_ck804;
34 extern unsigned bus_type[256];
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
42 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
44 mptable_init(mc, "A8N-E ", LAPIC_ADDR);
46 smp_write_processors(mc);
51 /* Bus: Bus ID Type */
52 /* Define numbers for PCI and ISA bus. */
53 for (bus_num = 0; bus_num < 256; bus_num++) {
54 if (bus_type[bus_num])
55 smp_write_bus(mc, bus_num, "PCI ");
57 smp_write_bus(mc, bus_isa, "ISA ");
59 /* I/O APICs: APIC ID Version State Address */
65 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
67 res = find_resource(dev, PCI_BASE_ADDRESS_1);
69 smp_write_ioapic(mc, apicid_ck804, 0x11,
73 /* Initialize interrupt mapping. */
75 pci_write_config32(dev, 0x7c, dword);
78 pci_write_config32(dev, 0x80, dword);
81 pci_write_config32(dev, 0x84, dword);
86 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
88 // Onboard ck804 smbus
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
90 bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
93 // Onboard ck804 USB 1.1
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
95 bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
98 // Onboard ck804 USB 2
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
100 bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
103 // Onboard ck804 SATA 0
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
105 bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
108 // Onboard ck804 SATA 1
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
110 bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
115 bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
118 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
119 smp_write_lintsrc(mc, mp_ExtINT,
120 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
121 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
122 smp_write_lintsrc(mc, mp_NMI,
123 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
124 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
126 /* There is no extension information... */
128 /* Compute the checksums. */
130 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
131 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
132 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
133 mc, smp_next_mpe_entry(mc));
134 return smp_next_mpe_entry(mc);
137 unsigned long write_smp_table(unsigned long addr)
139 void *v = smp_write_floating_table(addr);
140 return (unsigned long)smp_write_config_table(v);