2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_isa;
32 extern unsigned char bus_ck804[6];
33 extern unsigned apicid_ck804;
34 extern unsigned bus_type[256];
35 extern void get_bus_conf(void);
37 static void *smp_write_config_table(void *v)
39 static const char sig[4] = "PCMP";
40 static const char oem[8] = "ASUS ";
41 static const char productid[12] = "A8N-E ";
42 struct mp_config_table *mc;
46 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
47 memset(mc, 0, sizeof(*mc));
49 memcpy(mc->mpc_signature, sig, sizeof(sig));
50 mc->mpc_length = sizeof(*mc); /* initially just the header */
52 mc->mpc_checksum = 0; /* not yet computed */
53 memcpy(mc->mpc_oem, oem, sizeof(oem));
54 memcpy(mc->mpc_productid, productid, sizeof(productid));
57 mc->mpc_entry_count = 0; /* No entries yet... */
58 mc->mpc_lapic = LAPIC_ADDR;
63 smp_write_processors(mc);
68 /* Bus: Bus ID Type */
69 /* Define numbers for PCI and ISA bus. */
70 for (bus_num = 0; bus_num < 256; bus_num++) {
71 if (bus_type[bus_num])
72 smp_write_bus(mc, bus_num, "PCI ");
74 smp_write_bus(mc, bus_isa, "ISA ");
76 /* I/O APICs: APIC ID Version State Address */
82 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
84 res = find_resource(dev, PCI_BASE_ADDRESS_1);
86 smp_write_ioapic(mc, apicid_ck804, 0x11,
90 /* Initialize interrupt mapping. */
92 pci_write_config32(dev, 0x7c, dword);
95 pci_write_config32(dev, 0x80, dword);
98 pci_write_config32(dev, 0x84, dword);
103 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
104 smp_write_intsrc(mc, mp_ExtINT,
105 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
106 bus_isa, 0x0, apicid_ck804, 0x0);
107 smp_write_intsrc(mc, mp_INT,
108 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
109 bus_isa, 0x1, apicid_ck804, 0x1);
110 smp_write_intsrc(mc, mp_INT,
111 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
112 bus_isa, 0x0, apicid_ck804, 0x2);
113 smp_write_intsrc(mc, mp_INT,
114 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
115 bus_isa, 0x4, apicid_ck804, 0x4);
116 smp_write_intsrc(mc, mp_INT,
117 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
118 bus_isa, 0x6, apicid_ck804, 0x6);
119 smp_write_intsrc(mc, mp_INT,
120 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
121 bus_isa, 0x7, apicid_ck804, 0x7);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
123 bus_isa, 0x8, apicid_ck804, 0x8);
124 smp_write_intsrc(mc, mp_INT,
125 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
126 bus_isa, 0x9, apicid_ck804, 0x9);
127 smp_write_intsrc(mc, mp_INT,
128 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
129 bus_isa, 0xa, apicid_ck804, 0xa);
130 smp_write_intsrc(mc, mp_INT,
131 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
132 bus_isa, 0xc, apicid_ck804, 0xc);
133 smp_write_intsrc(mc, mp_INT,
134 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
135 bus_isa, 0xd, apicid_ck804, 0xd);
136 smp_write_intsrc(mc, mp_INT,
137 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
138 bus_isa, 0xe, apicid_ck804, 0xe);
139 smp_write_intsrc(mc, mp_INT,
140 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
141 bus_isa, 0xf, apicid_ck804, 0xf);
143 // Onboard ck804 smbus
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
145 bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
148 // Onboard ck804 USB 1.1
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
150 bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
153 // Onboard ck804 USB 2
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
155 bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
158 // Onboard ck804 SATA 0
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
160 bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
163 // Onboard ck804 SATA 1
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
165 bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
170 bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
173 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
174 smp_write_intsrc(mc, mp_ExtINT,
175 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
176 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
177 smp_write_intsrc(mc, mp_NMI,
178 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
179 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
181 /* There is no extension information... */
183 /* Compute the checksums. */
185 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
186 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
187 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
188 mc, smp_next_mpe_entry(mc));
189 return smp_next_mpe_entry(mc);
192 unsigned long write_smp_table(unsigned long addr)
194 void *v = smp_write_floating_table(addr);
195 return (unsigned long)smp_write_config_table(v);