2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 ## (Thanks to LSRA University of Mannheim for their support)
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
25 default CONFIG_XIP_ROM_SIZE = 64 * 1024
26 include /config/failovercalculation.lb
30 # Needed by irq_tables and mptable and acpi_tables.
32 if CONFIG_GENERATE_MP_TABLE object mptable.o end
33 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
36 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
37 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
41 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
42 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
43 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
44 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
47 if CONFIG_HAVE_FAILOVER_BOOT
48 if CONFIG_USE_FAILOVER_IMAGE
49 mainboardinit cpu/x86/16bit/entry16.inc
50 ldscript /cpu/x86/16bit/entry16.lds
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/entry16.inc
55 ldscript /cpu/x86/16bit/entry16.lds
58 mainboardinit cpu/x86/32bit/entry32.inc
60 ldscript /cpu/x86/32bit/entry32.lds
61 ldscript /cpu/amd/car/cache_as_ram.lds
63 if CONFIG_HAVE_FAILOVER_BOOT
64 if CONFIG_USE_FAILOVER_IMAGE
65 mainboardinit cpu/x86/16bit/reset16.inc
66 ldscript /cpu/x86/16bit/reset16.lds
68 mainboardinit cpu/x86/32bit/reset32.inc
69 ldscript /cpu/x86/32bit/reset32.lds
72 if CONFIG_USE_FALLBACK_IMAGE
73 mainboardinit cpu/x86/16bit/reset16.inc
74 ldscript /cpu/x86/16bit/reset16.lds
76 mainboardinit cpu/x86/32bit/reset32.inc
77 ldscript /cpu/x86/32bit/reset32.lds
80 # Include an ID string (for safe flashing).
81 mainboardinit arch/i386/lib/id.inc
82 ldscript /arch/i386/lib/id.lds
83 # ROMSTRAP table for CK804.
84 if CONFIG_HAVE_FAILOVER_BOOT
85 if CONFIG_USE_FAILOVER_IMAGE
86 mainboardinit southbridge/nvidia/ck804/romstrap.inc
87 ldscript /southbridge/nvidia/ck804/romstrap.lds
90 if CONFIG_USE_FALLBACK_IMAGE
91 mainboardinit southbridge/nvidia/ck804/romstrap.inc
92 ldscript /southbridge/nvidia/ck804/romstrap.lds
95 mainboardinit cpu/amd/car/cache_as_ram.inc
96 if CONFIG_HAVE_FAILOVER_BOOT
97 if CONFIG_USE_FAILOVER_IMAGE
98 ldscript /arch/i386/lib/failover_failover.lds
101 if CONFIG_USE_FALLBACK_IMAGE
102 ldscript /arch/i386/lib/failover.lds
108 mainboardinit ./auto.inc
112 chip northbridge/amd/amdk8/root_complex # Root complex
113 device apic_cluster 0 on # APIC cluster
114 chip cpu/amd/socket_939 # Socket 939 CPU
115 device apic 0 on end # APIC
119 device pci_domain 0 on # PCI domain
120 chip northbridge/amd/amdk8 # mc0
121 device pci 18.0 on # Northbridge
122 # Devices on link 0, link 0 == LDT 0
123 chip southbridge/nvidia/ck804 # Southbridge
124 device pci 0.0 on end # HT
125 device pci 1.0 on # LPC
126 chip superio/ite/it8712f # Super I/O
127 device pnp 2e.0 on # Floppy
132 device pnp 2e.1 on # Com1
136 device pnp 2e.2 off # Com2 (N/A on this board)
140 device pnp 2e.3 on # Parallel port
145 device pnp 2e.4 on # Environment controller
150 device pnp 2e.5 on # PS/2 keyboard
156 device pnp 2e.6 on # PS/2 mouse
160 device pnp 2e.7 on # GPIO config
166 # GPIO Polarity for Set 3
168 # GPIO Pin Internal Pull up for Set 3
170 # Simple I/O register config
176 device pnp 2e.8 on # Midi port
180 device pnp 2e.9 on # Game port
183 device pnp 2e.a off # IR (N/A on this board)
189 device pci 1.1 on # SM 0
190 # chip drivers/generic/generic #dimm 0-0-0
191 # device i2c 50 on end
193 # chip drivers/generic/generic #dimm 0-0-1
194 # device i2c 51 on end
196 # chip drivers/generic/generic #dimm 0-1-0
197 # device i2c 52 on end
199 # chip drivers/generic/generic #dimm 0-1-1
200 # device i2c 53 on end
202 # chip drivers/generic/generic #dimm 1-0-0
203 # device i2c 54 on end
205 # chip drivers/generic/generic #dimm 1-0-1
206 # device i2c 55 on end
208 # chip drivers/generic/generic #dimm 1-1-0
209 # device i2c 56 on end
211 # chip drivers/generic/generic #dimm 1-1-1
212 # device i2c 57 on end
215 device pci 2.0 on end # USB 1.1
216 device pci 2.1 on end # USB 2
217 device pci 4.0 on end # Onboard audio (ACI)
218 device pci 4.1 off end # Onboard modem (MCI), N/A
219 device pci 6.0 on end # IDE
220 device pci 7.0 on end # SATA 1
221 device pci 8.0 on end # SATA 0
222 device pci 9.0 on end # PCI
223 device pci a.0 on end # NIC
224 device pci b.0 on end # PCI E 3
225 device pci c.0 on end # PCI E 2
226 device pci d.0 on end # PCI E 1
227 device pci e.0 on end # PCI E 0
228 register "ide0_enable" = "1"
229 register "ide1_enable" = "1"
230 register "sata0_enable" = "1"
231 register "sata1_enable" = "1"
232 # register "mac_eeprom_smbus" = "3"
233 # register "mac_eeprom_addr" = "0x51"
236 device pci 18.1 on end
237 device pci 18.2 on end
238 device pci 18.3 on end