src/mainboard/asrock/939a785gmh/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include <spd.h>
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  43 #include <usbdebug.h>
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47 #include "southbridge/amd/rs780/rs780_early_setup.c"
  48 #include "southbridge/amd/sb700/sb700_early_setup.c"
  49 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  52 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  55 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  56
  57 static inline int spd_read_byte(u32 device, u32 address)
  58 {
  59         return smbus_read_byte(device, address);
  60 }
  61
  62 #include "northbridge/amd/amdk8/amdk8.h"
  63 #include "northbridge/amd/amdk8/incoherent_ht.c"
  64 #include "northbridge/amd/amdk8/raminit.c"
  65 #include "northbridge/amd/amdk8/coherent_ht.c"
  66 #include "lib/generic_sdram.c"
  67 #include "resourcemap.c"
  68 #include "cpu/amd/dualcore/dualcore.c"
  69 #include "cpu/amd/car/post_cache_as_ram.c"
  70 #include "cpu/amd/model_fxx/init_cpus.c"
  71 #include "cpu/amd/model_fxx/fidvid.c"
  72 #include "northbridge/amd/amdk8/early_ht.c"
  73
  74 static void sio_init(void)
  75 {
  76         u8 reg;
  77
  78         pnp_enter_ext_func_mode(GPIO2345_DEV);
  79         pnp_set_logical_device(GPIO2345_DEV);
  80
  81         /* Pin 119 ~ 120 GP21, GP20  */
  82         reg = pnp_read_config(GPIO2345_DEV, 0x29);
  83         pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
  84
  85         /* Turn on the Power LED ("Suspend LED" in Super I/O) */
  86         reg = pnp_read_config(GPIO2345_DEV, 0xf3);
  87         pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
  88
  89         /* todo document this */
  90         pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
  91         pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
  92
  93 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
  94 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
  95
  96 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
  97 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
  98 //DDR voltage 44 45 46
  99
 100         /* GPO20 - sideport voltage GPO23 - mgpuV */
 101         pnp_write_config(GPIO2345_DEV, 0x30, 0x07);     /* Enable GPIO 2,3,4. */
 102         pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);     /* dir of GPIO2 11110110*/
 103         pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);     /* data */
 104         pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);     /* No inversion */
 105
 106         /* GPO30 GPO33 GPO35 */
 107         //GPO35 - loadline control 0 - enabled
 108         //GPIO30 - unknown
 109         //GPIO33 - unknown
 110         pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);     /* dir of GPIO3 11010110*/
 111         pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);     /* data */
 112         pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);     /* No inversion */
 113
 114         /* GPO40 GPO41 GPO42 GPO43 PO45 */
 115         pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);     /* dir of GPIO4 11010000 */
 116         pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);     /* data */
 117         pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);     /* No inversion */
 118
 119         pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);     /* MFC */
 120         pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);     /* MFC */
 121         pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);     /* trig type */
 122         pnp_exit_ext_func_mode(GPIO2345_DEV);
 123 }
 124
 125 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 126 {
 127         static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 128         int needs_reset = 0;
 129         u32 bsp_apicid = 0;
 130         msr_t msr;
 131         struct cpuid_result cpuid1;
 132         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 133
 134         if (!cpu_init_detectedx && boot_cpu()) {
 135                 /* Nothing special needs to be done to find bus 0 */
 136                 /* Allow the HT devices to be found */
 137                 enumerate_ht_chain();
 138                 /* sb700_lpc_port80(); */
 139                 sb700_pci_port80();
 140         }
 141
 142         if (bist == 0)
 143                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 144
 145         enable_rs780_dev8();
 146         sb700_lpc_init();
 147
 148         sio_init();
 149         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 150         uart_init();
 151
 152 #if CONFIG_USBDEBUG
 153         sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 154         early_usbdebug_init();
 155 #endif
 156
 157         console_init();
 158
 159         /* Halt if there was a built in self test failure */
 160         report_bist_failure(bist);
 161         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 162
 163         setup_939a785gmh_resource_map();
 164
 165         setup_coherent_ht_domain();
 166
 167 #if CONFIG_LOGICAL_CPUS==1
 168         /* It is said that we should start core1 after all core0 launched */
 169         wait_all_core0_started();
 170         start_other_cores();
 171 #endif
 172         wait_all_aps_started(bsp_apicid);
 173
 174         ht_setup_chains_x(sysinfo);
 175
 176         /* run _early_setup before soft-reset. */
 177         rs780_early_setup();
 178         sb700_early_setup();
 179
 180         /* Check to see if processor is capable of changing FIDVID  */
 181         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 182         cpuid1 = cpuid(0x80000007);
 183         if ((cpuid1.edx & 0x6) == 0x6) {
 184                 /* Read FIDVID_STATUS */
 185                 msr=rdmsr(0xc0010042);
 186                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 187
 188                 enable_fid_change();
 189                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 190                 init_fidvid_bsp(bsp_apicid);
 191
 192                 /* show final fid and vid */
 193                 msr=rdmsr(0xc0010042);
 194                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 195         } else {
 196                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 197         }
 198
 199         needs_reset = optimize_link_coherent_ht();
 200         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 201         rs780_htinit();
 202         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 203
 204         if (needs_reset) {
 205                 print_info("ht reset -\n");
 206                 soft_reset();
 207         }
 208
 209         allow_all_aps_stop(bsp_apicid);
 210
 211         /* It's the time to set ctrl now; */
 212         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 213                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 214         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 215         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 216
 217         rs780_before_pci_init();
 218         sb700_before_pci_init();
 219
 220         post_cache_as_ram();
 221 }