src/mainboard/asrock/939a785gmh/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include <spd.h>
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  43 #include <usbdebug.h>
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47 #include "southbridge/amd/rs780/rs780_early_setup.c"
  48 #include "southbridge/amd/sb700/sb700_early_setup.c"
  49 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  52 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
  53 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
  54
  55 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58 }
  59
  60 /* called in raminit_f.c */
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 /*called in raminit_f.c */
  66 static inline int spd_read_byte(u32 device, u32 address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #include "northbridge/amd/amdk8/amdk8.h"
  72 #include "northbridge/amd/amdk8/incoherent_ht.c"
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76 #include "resourcemap.c"
  77 #include "cpu/amd/dualcore/dualcore.c"
  78 #include "cpu/amd/car/post_cache_as_ram.c"
  79 #include "cpu/amd/model_fxx/init_cpus.c"
  80 #include "cpu/amd/model_fxx/fidvid.c"
  81 #include "northbridge/amd/amdk8/early_ht.c"
  82
  83 static void sio_init(void)
  84 {
  85         u8 reg;
  86
  87         pnp_enter_ext_func_mode(GPIO2345_DEV);
  88         pnp_set_logical_device(GPIO2345_DEV);
  89
  90         /* Pin 119 ~ 120 GP21, GP20  */
  91         reg = pnp_read_config(GPIO2345_DEV, 0x29);
  92         pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
  93
  94         /* todo document this */
  95         pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
  96         pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
  97
  98 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
  99 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
 100
 101 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
 102 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
 103 //DDR voltage 44 45 46
 104
 105         /* GPO20 - sideport voltage GPO23 - mgpuV */
 106         pnp_write_config(GPIO2345_DEV, 0x30, 0x07);     /* Enable GPIO 2,3,4. */
 107         pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);     /* dir of GPIO2 11110110*/
 108         pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);     /* data */
 109         pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);     /* No inversion */
 110
 111         /* GPO30 GPO33 GPO35 */
 112         //GPO35 - loadline control 0 - enabled
 113         //GPIO30 - unknown
 114         //GPIO33 - unknown
 115         pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);     /* dir of GPIO3 11010110*/
 116         pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);     /* data */
 117         pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);     /* No inversion */
 118
 119         /* GPO40 GPO41 GPO42 GPO43 PO45 */
 120         pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);     /* dir of GPIO4 11010000 */
 121         pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);     /* data */
 122         pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);     /* No inversion */
 123
 124         pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);     /* MFC */
 125         pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);     /* MFC */
 126         pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);     /* trig type */
 127         pnp_exit_ext_func_mode(GPIO2345_DEV);
 128 }
 129
 130 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 131 {
 132         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 133         int needs_reset = 0;
 134         u32 bsp_apicid = 0;
 135         msr_t msr;
 136         struct cpuid_result cpuid1;
 137         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 138
 139         if (!cpu_init_detectedx && boot_cpu()) {
 140                 /* Nothing special needs to be done to find bus 0 */
 141                 /* Allow the HT devices to be found */
 142                 enumerate_ht_chain();
 143
 144                 /* sb700_lpc_port80(); */
 145                 sb700_pci_port80();
 146         }
 147
 148         if (bist == 0) {
 149                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 150         }
 151
 152         enable_rs780_dev8();
 153         sb700_lpc_init();
 154
 155         sio_init();
 156         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 157         uart_init();
 158
 159 #if CONFIG_USBDEBUG
 160         sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 161         early_usbdebug_init();
 162 #endif
 163
 164         console_init();
 165
 166         /* Halt if there was a built in self test failure */
 167         report_bist_failure(bist);
 168         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 169
 170         setup_939a785gmh_resource_map();
 171
 172         setup_coherent_ht_domain();
 173
 174 #if CONFIG_LOGICAL_CPUS==1
 175         /* It is said that we should start core1 after all core0 launched */
 176         wait_all_core0_started();
 177         start_other_cores();
 178 #endif
 179         wait_all_aps_started(bsp_apicid);
 180
 181         ht_setup_chains_x(sysinfo);
 182
 183         /* run _early_setup before soft-reset. */
 184         rs780_early_setup();
 185         sb700_early_setup();
 186
 187         /* Check to see if processor is capable of changing FIDVID  */
 188         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 189         cpuid1 = cpuid(0x80000007);
 190         if( (cpuid1.edx & 0x6) == 0x6 ) {
 191
 192                 /* Read FIDVID_STATUS */
 193                 msr=rdmsr(0xc0010042);
 194                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 195
 196                 enable_fid_change();
 197                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 198                 init_fidvid_bsp(bsp_apicid);
 199
 200                 /* show final fid and vid */
 201                 msr=rdmsr(0xc0010042);
 202                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 203
 204         } else {
 205                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 206         }
 207
 208         needs_reset = optimize_link_coherent_ht();
 209         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 210         rs780_htinit();
 211         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 212
 213         if (needs_reset) {
 214                 print_info("ht reset -\n");
 215                 soft_reset();
 216         }
 217
 218         allow_all_aps_stop(bsp_apicid);
 219
 220         /* It's the time to set ctrl now; */
 221         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 222                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 223         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 224         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 225
 226         rs780_before_pci_init();
 227         sb700_before_pci_init();
 228
 229         post_cache_as_ram();
 230 }