src/mainboard/asrock/939a785gmh/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include <spd.h>
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "superio/winbond/w83627dhg/early_serial.c"
  43 #include <usbdebug.h>
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47 #include "southbridge/amd/rs780/early_setup.c"
  48 #include "southbridge/amd/sb700/early_setup.c"
  49 #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  52 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  55 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  56
  57 static inline int spd_read_byte(u32 device, u32 address)
  58 {
  59         return smbus_read_byte(device, address);
  60 }
  61
  62 #include "northbridge/amd/amdk8/amdk8.h"
  63 #include "northbridge/amd/amdk8/incoherent_ht.c"
  64 #include "northbridge/amd/amdk8/raminit.c"
  65 #include "northbridge/amd/amdk8/coherent_ht.c"
  66 #include "lib/generic_sdram.c"
  67 #include "resourcemap.c"
  68 #include "cpu/amd/dualcore/dualcore.c"
  69 #include "cpu/amd/car/post_cache_as_ram.c"
  70 #include "cpu/amd/model_fxx/init_cpus.c"
  71 #include "cpu/amd/model_fxx/fidvid.c"
  72 #include "northbridge/amd/amdk8/early_ht.c"
  73
  74 static void sio_init(void)
  75 {
  76         u8 reg;
  77
  78         pnp_enter_ext_func_mode(GPIO2345_DEV);
  79         pnp_set_logical_device(GPIO2345_DEV);
  80
  81         /* Pin 119 ~ 120 is GP21, GP20  */
  82         reg = pnp_read_config(GPIO2345_DEV, 0x29);
  83         pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
  84
  85         /* Turn on the Power LED ("Suspend LED" in Super I/O) */
  86         reg = pnp_read_config(GPIO2345_DEV, 0xf3);
  87         pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
  88
  89         /* todo document this */
  90         pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
  91         pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
  92
  93         /* GPO20 - sideport voltage 1 = 1.82 0 = 1.92
  94            GPI21 - unknown input (NC?)
  95            GPI22 - unknown input (NC?)
  96            GPO23 - mgpuV bit0
  97            GP24-27 - PS/2 mouse/keyb (only keyb is connected use flip interface for mouse)
  98         */
  99         pnp_write_config(GPIO2345_DEV, 0x30, 0x07);     /* Enable GPIO 2,3,4. */
 100         pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);     /* dir of GPIO2 11110110*/
 101         pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);     /* data */
 102         pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);     /* No inversion */
 103
 104         /* GPIO30 - unknown output, set to 0
 105            GPI31 - unknown input NC?
 106            GPI32 - unknown input NC?
 107            GPIO33 - unknown output, set to 0.
 108            GPI34 - unknown input NC?
 109            GPO35 - loadline control 1 = enabled (2 phase clock) 0 = disabled 4 phase clock
 110            GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
 111            GP37 - unknown input NC? */
 112
 113         pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);     /* dir of GPIO3 11010110*/
 114         pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);     /* data */
 115         pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);     /* No inversion */
 116
 117         /* GPO40 - mgpuV bit2
 118            GPO41 - mgpuV bit1
 119            GPO42  - IRTX
 120            GPO43  - IRRX
 121            GPIO44 - memory voltage bit2 (input/outputlow)
 122            GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
 123            GPIO46 - memory voltage bit0
 124            GPIO47 - unknown input? */
 125
 126         pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);     /* dir of GPIO4 11010000 */
 127         pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);     /* data */
 128         pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);     /* No inversion */
 129
 130         pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);     /* MFC */
 131         pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);     /* MFC */
 132         pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);     /* trig type */
 133         pnp_exit_ext_func_mode(GPIO2345_DEV);
 134 }
 135
 136 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 137 {
 138         static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 139         int needs_reset = 0;
 140         u32 bsp_apicid = 0;
 141         msr_t msr;
 142         struct cpuid_result cpuid1;
 143         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 144
 145         if (!cpu_init_detectedx && boot_cpu()) {
 146                 /* Nothing special needs to be done to find bus 0 */
 147                 /* Allow the HT devices to be found */
 148                 enumerate_ht_chain();
 149                 /* sb700_lpc_port80(); */
 150                 sb700_pci_port80();
 151         }
 152
 153         if (bist == 0)
 154                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 155
 156         enable_rs780_dev8();
 157         sb700_lpc_init();
 158
 159         sio_init();
 160         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 161         uart_init();
 162
 163 #if CONFIG_USBDEBUG
 164         sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 165         early_usbdebug_init();
 166 #endif
 167
 168         console_init();
 169
 170         /* Halt if there was a built in self test failure */
 171         report_bist_failure(bist);
 172         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 173
 174         setup_939a785gmh_resource_map();
 175
 176         setup_coherent_ht_domain();
 177
 178 #if CONFIG_LOGICAL_CPUS==1
 179         /* It is said that we should start core1 after all core0 launched */
 180         wait_all_core0_started();
 181         start_other_cores();
 182 #endif
 183         wait_all_aps_started(bsp_apicid);
 184
 185         ht_setup_chains_x(sysinfo);
 186
 187         /* run _early_setup before soft-reset. */
 188         rs780_early_setup();
 189         sb700_early_setup();
 190
 191         /* Check to see if processor is capable of changing FIDVID  */
 192         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 193         cpuid1 = cpuid(0x80000007);
 194         if ((cpuid1.edx & 0x6) == 0x6) {
 195                 /* Read FIDVID_STATUS */
 196                 msr=rdmsr(0xc0010042);
 197                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 198
 199                 enable_fid_change();
 200                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 201                 init_fidvid_bsp(bsp_apicid);
 202
 203                 /* show final fid and vid */
 204                 msr=rdmsr(0xc0010042);
 205                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 206         } else {
 207                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 208         }
 209
 210         needs_reset = optimize_link_coherent_ht();
 211         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 212         rs780_htinit();
 213         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 214
 215         if (needs_reset) {
 216                 print_info("ht reset -\n");
 217                 soft_reset();
 218         }
 219
 220         allow_all_aps_stop(bsp_apicid);
 221
 222         /* It's the time to set ctrl now; */
 223         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 224                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 225         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 226         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 227
 228         rs780_before_pci_init();
 229         sb700_before_pci_init();
 230
 231         post_cache_as_ram();
 232 }