1 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_ROM_PAYLOAD
7 uses CONFIG_IRQ_SLOT_COUNT
9 uses CONFIG_MAINBOARD_VENDOR
10 uses CONFIG_MAINBOARD_PART_NUMBER
11 uses COREBOOT_EXTRA_VERSION
13 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_STACK_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_IMAGE_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_SECTION_OFFSET
21 uses CONFIG_ROM_PAYLOAD_START
23 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_PAYLOAD_SIZE
29 uses CONFIG_XIP_ROM_SIZE
30 uses CONFIG_XIP_ROM_BASE
31 uses CONFIG_CROSS_COMPILE
35 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
36 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
37 uses CONFIG_CONSOLE_SERIAL8250
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_UDELAY_TSC
42 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
43 # uses CONFIG_CONSOLE_VGA
44 # uses CONFIG_PCI_ROM_RUN
46 uses CONFIG_PIRQ_ROUTE
48 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
49 default CONFIG_ROM_SIZE = 256 * 1024
56 ## Build code for the fallback boot
58 default CONFIG_HAVE_FALLBACK_BOOT=1
61 ## Build code to reset the motherboard from coreboot
63 default CONFIG_HAVE_HARD_RESET=0
65 ## Delay timer options
67 default CONFIG_UDELAY_TSC=1
68 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
71 ## Build code to export a programmable irq routing table
73 default CONFIG_HAVE_PIRQ_TABLE=1
74 default CONFIG_IRQ_SLOT_COUNT=5 # TODO?
75 default CONFIG_PIRQ_ROUTE=1
78 ## Build code to export a CMOS option table
80 # default CONFIG_HAVE_OPTION_TABLE=0
83 ### coreboot layout values
86 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
87 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
88 default CONFIG_FALLBACK_SIZE = 128 * 1024
91 ## Use a small 8K stack
93 default CONFIG_STACK_SIZE=0x2000
96 ## Use a small 16K heap
98 default CONFIG_HEAP_SIZE=0x4000
101 ## Only use the option table in a normal image
103 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
104 # default CONFIG_USE_OPTION_TABLE = 0
106 default CONFIG_RAMBASE = 0x00004000
108 default CONFIG_ROM_PAYLOAD = 1
111 ## The default compiler
113 default CONFIG_CROSS_COMPILE=""
114 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
118 ## The Serial Console
121 # To Enable the Serial Console
122 default CONFIG_CONSOLE_SERIAL8250=1
124 ## Select the serial console baud rate
125 default CONFIG_TTYS0_BAUD=115200
126 #default CONFIG_TTYS0_BAUD=57600
127 #default CONFIG_TTYS0_BAUD=38400
128 #default CONFIG_TTYS0_BAUD=19200
129 #default CONFIG_TTYS0_BAUD=9600
130 #default CONFIG_TTYS0_BAUD=4800
131 #default CONFIG_TTYS0_BAUD=2400
132 #default CONFIG_TTYS0_BAUD=1200
134 # Select the serial console base port
135 default CONFIG_TTYS0_BASE=0x3f8
137 # Select the serial protocol
138 # This defaults to 8 data bits, 1 stop bit, and no parity
139 default CONFIG_TTYS0_LCS=0x3
142 ### Select the coreboot loglevel
144 ## EMERG 1 system is unusable
145 ## ALERT 2 action must be taken immediately
146 ## CRIT 3 critical conditions
147 ## ERR 4 error conditions
148 ## WARNING 5 warning conditions
149 ## NOTICE 6 normal but significant condition
150 ## INFO 7 informational
151 ## CONFIG_DEBUG 8 debug-level messages
152 ## SPEW 9 Way too many details
154 ## Request this level of debugging output
155 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
156 ## At a maximum only compile in this level of debugging
157 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
160 # default CONFIG_CONSOLE_VGA=1
161 # default CONFIG_PCI_ROM_RUN=1
162 default CONFIG_VIDEO_MB = 0
169 default CONFIG_CBFS=0