4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_ROM_PAYLOAD
13 uses MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
23 uses ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
38 uses DEFAULT_CONSOLE_LOGLEVEL
39 uses MAXIMUM_CONSOLE_LOGLEVEL
40 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_UDELAY_TSC
45 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
46 uses CONFIG_CONSOLE_VGA
47 uses CONFIG_PCI_ROM_RUN
52 uses CONFIG_USE_PRINTK_IN_CAR
55 ## ROM_SIZE is the size of boot ROM that this board will use.
56 default ROM_SIZE = 256*1024
61 default CONFIG_CONSOLE_VGA=0
62 default CONFIG_PCI_ROM_RUN=0
63 default CONFIG_VIDEO_MB=8
66 ## Build code for the fallback boot
68 default HAVE_FALLBACK_BOOT=1
73 default HAVE_MP_TABLE=0
76 ## Build code to reset the motherboard from coreboot
78 default HAVE_HARD_RESET=0
80 ## Delay timer options
82 default CONFIG_UDELAY_TSC=1
83 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
86 ## Build code to export a programmable irq routing table
88 default HAVE_PIRQ_TABLE=1
89 default IRQ_SLOT_COUNT=3
94 ## Build code to export a CMOS option table
96 default HAVE_OPTION_TABLE=0
99 ### coreboot layout values
102 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
103 default ROM_IMAGE_SIZE = 65536
104 default FALLBACK_SIZE = 131072
107 ## enable CACHE_AS_RAM specifics
109 default USE_DCACHE_RAM=1
110 default DCACHE_RAM_BASE=0xc8000
111 default DCACHE_RAM_SIZE=0x08000
112 default CONFIG_USE_PRINTK_IN_CAR=1
115 ## Use a small 8K stack
117 default STACK_SIZE=0x2000
120 ## Use a small 16K heap
122 default HEAP_SIZE=0x4000
125 ## Only use the option table in a normal image
127 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
128 default USE_OPTION_TABLE = 0
130 default _RAMBASE = 0x00004000
132 default CONFIG_ROM_PAYLOAD = 1
135 ## The default compiler
137 default CROSS_COMPILE=""
138 default CC="$(CROSS_COMPILE)gcc -m32"
142 ## The Serial Console
145 # To Enable the Serial Console
146 default CONFIG_CONSOLE_SERIAL8250=1
148 ## Select the serial console baud rate
149 default TTYS0_BAUD=115200
150 #default TTYS0_BAUD=57600
151 #default TTYS0_BAUD=38400
152 #default TTYS0_BAUD=19200
153 #default TTYS0_BAUD=9600
154 #default TTYS0_BAUD=4800
155 #default TTYS0_BAUD=2400
156 #default TTYS0_BAUD=1200
158 # Select the serial console base port
159 default TTYS0_BASE=0x3f8
161 # Select the serial protocol
162 # This defaults to 8 data bits, 1 stop bit, and no parity
163 default TTYS0_LCS=0x3
166 ### Select the coreboot loglevel
168 ## EMERG 1 system is unusable
169 ## ALERT 2 action must be taken immediately
170 ## CRIT 3 critical conditions
171 ## ERR 4 error conditions
172 ## WARNING 5 warning conditions
173 ## NOTICE 6 normal but significant condition
174 ## INFO 7 informational
175 ## DEBUG 8 debug-level messages
176 ## SPEW 9 Way too many details
178 ## Request this level of debugging output
179 default DEFAULT_CONSOLE_LOGLEVEL=8
180 ## At a maximum only compile in this level of debugging
181 default MAXIMUM_CONSOLE_LOGLEVEL=8
188 default CONFIG_CBFS=0