src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  22
  23 #include "cpu/x86/mtrr/earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #include "northbridge/amd/amdk8/setup_resource_map.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  29
  30 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  31
  32 /*
  33  * GPIO28 of 8111 will control H0_MEMRESET_L
  34  * GPIO29 of 8111 will control H1_MEMRESET_L
  35  */
  36 static void memreset_setup(void)
  37 {
  38         if (is_cpu_pre_c0()) {
  39                 /* Set the memreset low */
  40                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  41                 /* Ensure the BIOS has control of the memory lines */
  42                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  43         }
  44         else {
  45                 /* Ensure the CPU has controll of the memory lines */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  47         }
  48 }
  49
  50 static void memreset(int controllers, const struct mem_controller *ctrl)
  51 {
  52         if (is_cpu_pre_c0()) {
  53                 udelay(800);
  54                 /* Set memreset_high */
  55                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  56                 udelay(90);
  57         }
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70
  71 #include "northbridge/amd/amdk8/raminit.c"
  72 #include "northbridge/amd/amdk8/resourcemap.c"
  73 #include "northbridge/amd/amdk8/coherent_ht.c"
  74 #include "lib/generic_sdram.c"
  75
  76 #include "cpu/amd/dualcore/dualcore.c"
  77
  78 #include "cpu/amd/car/post_cache_as_ram.c"
  79
  80 #include "cpu/amd/model_fxx/init_cpus.c"
  81
  82 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  83 #include "northbridge/amd/amdk8/early_ht.c"
  84
  85 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  86 {
  87         static const uint16_t spd_addr [] = {
  88                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  89                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  90 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  91                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  92                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  93 #endif
  94         };
  95
  96         int needs_reset;
  97         unsigned bsp_apicid = 0;
  98         struct mem_controller ctrl[8];
  99         unsigned nodes;
 100
 101         if (!cpu_init_detectedx && boot_cpu()) {
 102                 /* Nothing special needs to be done to find bus 0 */
 103                 /* Allow the HT devices to be found */
 104
 105                 enumerate_ht_chain();
 106
 107                 amd8111_enable_rom();
 108         }
 109
 110         if (bist == 0) {
 111                 bsp_apicid = init_cpus(cpu_init_detectedx);
 112         }
 113
 114         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 115         uart_init();
 116         console_init();
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         setup_default_resource_map();
 122
 123         needs_reset = setup_coherent_ht_domain();
 124
 125 #if CONFIG_LOGICAL_CPUS==1
 126         // It is said that we should start core1 after all core0 launched
 127         start_other_cores();
 128         wait_all_other_cores_started(bsp_apicid);
 129 #endif
 130         /* This is needed to be able to call udelay().  It could be moved to
 131          * memreset_setup, since udelay is called in memreset. */
 132         init_timer();
 133
 134         // automatically set that for you, but you might meet tight space
 135         needs_reset |= ht_setup_chains_x();
 136
 137         if (needs_reset) {
 138                 print_info("ht reset -\n");
 139                 soft_reset();
 140         }
 141
 142         allow_all_aps_stop(bsp_apicid);
 143
 144         nodes = get_nodes();
 145
 146         fill_mem_ctrl(nodes, ctrl, spd_addr);
 147
 148         enable_smbus();
 149
 150         memreset_setup();
 151
 152         sdram_initialize(nodes, ctrl);
 153
 154         post_cache_as_ram();
 155 }
 156