src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <cpu/amd/model_fxx_rev.h>
  11 #include "northbridge/amd/amdk8/incoherent_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/amd/model_fxx/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "northbridge/amd/amdk8/debug.c"
  19 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  20 #include "cpu/x86/mtrr/earlymtrr.c"
  21 #include "cpu/x86/bist.h"
  22 #include "northbridge/amd/amdk8/setup_resource_map.c"
  23 #include <spd.h>
  24 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  27
  28 /*
  29  * GPIO28 of 8111 will control H0_MEMRESET_L
  30  * GPIO29 of 8111 will control H1_MEMRESET_L
  31  */
  32 static void memreset_setup(void)
  33 {
  34         if (is_cpu_pre_c0()) {
  35                 /* Set the memreset low. */
  36                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  37                 /* Ensure the BIOS has control of the memory lines. */
  38                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  39         } else {
  40                 /* Ensure the CPU has control of the memory lines. */
  41                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  42         }
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47         if (is_cpu_pre_c0()) {
  48                 udelay(800);
  49                 /* Set memreset high. */
  50                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  51                 udelay(90);
  52         }
  53 }
  54
  55 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  56
  57 static inline int spd_read_byte(unsigned device, unsigned address)
  58 {
  59         return smbus_read_byte(device, address);
  60 }
  61
  62 #include "northbridge/amd/amdk8/raminit.c"
  63 #include "northbridge/amd/amdk8/resourcemap.c"
  64 #include "northbridge/amd/amdk8/coherent_ht.c"
  65 #include "lib/generic_sdram.c"
  66 #include "cpu/amd/dualcore/dualcore.c"
  67 #include "cpu/amd/car/post_cache_as_ram.c"
  68 #include "cpu/amd/model_fxx/init_cpus.c"
  69 #include "northbridge/amd/amdk8/early_ht.c"
  70
  71 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  72 {
  73         static const uint16_t spd_addr [] = {
  74                 DIMM0, DIMM2, 0, 0,
  75                 DIMM1, DIMM3, 0, 0,
  76 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  77                 DIMM4, DIMM6, 0, 0,
  78                 DIMM5, DIMM7, 0, 0,
  79 #endif
  80         };
  81
  82         int needs_reset;
  83         unsigned bsp_apicid = 0, nodes;
  84         struct mem_controller ctrl[8];
  85
  86         if (!cpu_init_detectedx && boot_cpu()) {
  87                 /* Nothing special needs to be done to find bus 0 */
  88                 /* Allow the HT devices to be found */
  89                 enumerate_ht_chain();
  90         }
  91
  92         if (bist == 0)
  93                 bsp_apicid = init_cpus(cpu_init_detectedx);
  94
  95         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  96         uart_init();
  97         console_init();
  98
  99         /* Halt if there was a built in self test failure */
 100         report_bist_failure(bist);
 101
 102         setup_default_resource_map();
 103
 104         needs_reset = setup_coherent_ht_domain();
 105
 106 #if CONFIG_LOGICAL_CPUS==1
 107         // It is said that we should start core1 after all core0 launched
 108         start_other_cores();
 109         wait_all_other_cores_started(bsp_apicid);
 110 #endif
 111         /* This is needed to be able to call udelay().  It could be moved to
 112          * memreset_setup, since udelay is called in memreset. */
 113         init_timer();
 114
 115         // automatically set that for you, but you might meet tight space
 116         needs_reset |= ht_setup_chains_x();
 117
 118         if (needs_reset) {
 119                 print_info("ht reset -\n");
 120                 soft_reset();
 121         }
 122
 123         allow_all_aps_stop(bsp_apicid);
 124
 125         nodes = get_nodes();
 126
 127         fill_mem_ctrl(nodes, ctrl, spd_addr);
 128
 129         enable_smbus();
 130
 131         memreset_setup();
 132
 133         sdram_initialize(nodes, ctrl);
 134
 135         post_cache_as_ram();
 136 }