1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/x86/lapic.h>
11 #define HT_INIT_CONTROL 0x6c
12 #define HTIC_BIOSR_Detect (1<<5)
14 /* If we assume a symmetric processor configuration we can
15 * get all of the information we need to write the processor
16 * entry from the bootstrap processor.
17 * Plus I don't think linux really even cares.
18 * Having the proper apicid's in the table so the non-bootstrap
19 * processors can be woken up should be enough. Linux-2.6.11 work-around.
21 static void smp_write_processors_inorder(struct mp_config_table *mc)
25 unsigned apic_version;
26 unsigned cpu_features;
27 unsigned cpu_feature_flags;
28 struct cpuid_result result;
31 boot_apic_id = lapicid();
32 apic_version = lapic_read(LAPIC_LVR) & 0xff;
34 cpu_features = result.eax;
35 cpu_feature_flags = result.edx;
36 /* order the output of the cpus to fix a bug in kernel 6 11 */
37 for(order_id = 0;order_id <256; order_id++) {
38 for(cpu = all_devices; cpu; cpu = cpu->next) {
39 unsigned long cpu_flag;
40 if ((cpu->path.type != DEVICE_PATH_APIC) ||
41 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
48 cpu_flag = MPC_CPU_ENABLED;
49 if (boot_apic_id == cpu->path.apic.apic_id) {
50 cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
52 if(cpu->path.apic.apic_id == order_id) {
53 smp_write_processor(mc,
54 cpu->path.apic.apic_id, apic_version,
55 cpu_flag, cpu_features, cpu_feature_flags);
62 static unsigned node_link_to_bus(unsigned node, unsigned link)
67 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
71 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
76 config_map = pci_read_config32(dev, reg);
77 if ((config_map & 3) != 3) {
80 dst_node = (config_map >> 4) & 7;
81 dst_link = (config_map >> 8) & 3;
82 bus_base = (config_map >> 16) & 0xff;
84 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
85 dst_node, dst_link, bus_base,
88 if ((dst_node == node) && (dst_link == link))
96 static unsigned max_apicid(void)
101 for(dev = all_devices; dev; dev = dev->next) {
102 if (dev->path.type != DEVICE_PATH_APIC)
104 if (dev->path.apic.apic_id > max) {
105 max = dev->path.apic.apic_id;
111 static void *smp_write_config_table(void *v)
113 struct mp_config_table *mc;
114 unsigned char bus_num;
115 unsigned char bus_isa;
116 unsigned char bus_chain_0;
117 unsigned char bus_8131_1;
118 unsigned char bus_8131_2;
119 unsigned char bus_8111_1;
120 unsigned apicid_base;
121 unsigned apicid_8111;
122 unsigned apicid_8131_1;
123 unsigned apicid_8131_2;
125 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
127 mptable_init(mc, "HDAMA ", LAPIC_ADDR);
129 smp_write_processors_inorder(mc);
131 apicid_base = max_apicid() + 1;
132 apicid_8111 = apicid_base;
133 apicid_8131_1 = apicid_base + 1;
134 apicid_8131_2 = apicid_base + 2;
139 bus_chain_0 = node_link_to_bus(0, 0);
140 if (bus_chain_0 == 0xff) {
141 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
146 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
148 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
149 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
153 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
159 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
161 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
165 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
170 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
172 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
176 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
182 /* define bus and isa numbers */
183 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
184 smp_write_bus(mc, bus_num, "PCI ");
186 smp_write_bus(mc, bus_isa, "ISA ");
188 /* IOAPIC handling */
189 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
192 struct resource *res;
194 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
196 res = find_resource(dev, PCI_BASE_ADDRESS_0);
198 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
202 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1));
204 res = find_resource(dev, PCI_BASE_ADDRESS_0);
206 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
211 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
213 /* Standard local interrupt assignments */
214 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
215 bus_isa, 0x00, MP_APIC_ALL, 0x00);
216 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
217 bus_isa, 0x00, MP_APIC_ALL, 0x01);
219 /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
221 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13);
222 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13);
224 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11);
227 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11);
228 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12);
229 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13);
230 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10);
233 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12);
234 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13);
235 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10);
236 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11);
239 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11);
240 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12);
241 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13);
242 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10);
245 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12);
246 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13);
247 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10);
248 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11);
251 // FIXME get the irqs right, it's just hacked to work for now
252 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11);
253 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12);
254 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13);
255 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10);
258 // FIXME get the irqs right, it's just hacked to work for now
259 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10);
260 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11);
261 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12);
262 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13);
264 /* There is no extension information... */
266 /* Compute the checksums */
267 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
268 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
269 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
270 mc, smp_next_mpe_entry(mc));
271 return smp_next_mpe_entry(mc);
274 static void reboot_if_hotswap(void)
276 /* Hack patch work around for hot swap enable 33mhz problem */
282 unsigned bus_chain_0 = node_link_to_bus(0, 0);
285 printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
286 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
288 printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
290 data = pci_read_config32(dev, 0xa0);
291 if(!(((data>>16)&0x03)==0x03)) {
293 printk(BIOS_DEBUG, "Bad PCIX MHz - Reset\n");
296 printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
297 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
299 printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
301 data = pci_read_config32(dev, 0x48);
304 printk(BIOS_DEBUG, "Bad Hot Swap start - Reset\n");
309 dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3));
310 pci_write_config8(dev, 0x41, 0xf1);
312 dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
313 htic = pci_read_config32(dev, HT_INIT_CONTROL);
314 htic &= ~HTIC_BIOSR_Detect;
315 pci_write_config32(dev, HT_INIT_CONTROL, htic);
319 printk(BIOS_DEBUG, "OK 133MHz & Hot Swap is off\n");
323 unsigned long write_smp_table(unsigned long addr)
328 v = smp_write_floating_table(addr);
329 return (unsigned long)smp_write_config_table(v);