1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/x86/lapic.h>
11 #define HT_INIT_CONTROL 0x6c
12 #define HTIC_BIOSR_Detect (1<<5)
14 static unsigned node_link_to_bus(unsigned node, unsigned link)
19 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
23 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
28 config_map = pci_read_config32(dev, reg);
29 if ((config_map & 3) != 3) {
32 dst_node = (config_map >> 4) & 7;
33 dst_link = (config_map >> 8) & 3;
34 bus_base = (config_map >> 16) & 0xff;
36 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
37 dst_node, dst_link, bus_base,
40 if ((dst_node == node) && (dst_link == link))
48 static unsigned max_apicid(void)
53 for(dev = all_devices; dev; dev = dev->next) {
54 if (dev->path.type != DEVICE_PATH_APIC)
56 if (dev->path.apic.apic_id > max) {
57 max = dev->path.apic.apic_id;
63 static void *smp_write_config_table(void *v)
65 struct mp_config_table *mc;
67 unsigned char bus_chain_0;
68 unsigned char bus_8131_1;
69 unsigned char bus_8131_2;
70 unsigned char bus_8111_1;
73 unsigned apicid_8131_1;
74 unsigned apicid_8131_2;
76 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
78 mptable_init(mc, LAPIC_ADDR);
80 smp_write_processors(mc);
82 apicid_base = max_apicid() + 1;
83 apicid_8111 = apicid_base;
84 apicid_8131_1 = apicid_base + 1;
85 apicid_8131_2 = apicid_base + 2;
90 bus_chain_0 = node_link_to_bus(0, 0);
91 if (bus_chain_0 == 0xff) {
92 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
97 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
99 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
102 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
106 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
108 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
111 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
115 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
117 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
120 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
125 mptable_write_buses(mc, NULL, &bus_isa);
127 /* IOAPIC handling */
128 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
131 struct resource *res;
133 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
135 res = find_resource(dev, PCI_BASE_ADDRESS_0);
137 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
141 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1));
143 res = find_resource(dev, PCI_BASE_ADDRESS_0);
145 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
150 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
152 /* Standard local interrupt assignments */
153 mptable_lintsrc(mc, bus_isa);
155 /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11);
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12);
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12);
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11);
187 // FIXME get the irqs right, it's just hacked to work for now
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12);
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13);
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10);
194 // FIXME get the irqs right, it's just hacked to work for now
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10);
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12);
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13);
200 /* There is no extension information... */
202 /* Compute the checksums */
203 return mptable_finalize(mc);
206 static void reboot_if_hotswap(void)
208 /* Hack patch work around for hot swap enable 33mhz problem */
214 unsigned bus_chain_0 = node_link_to_bus(0, 0);
217 printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
218 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
220 printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
222 data = pci_read_config32(dev, 0xa0);
223 if(!(((data>>16)&0x03)==0x03)) {
225 printk(BIOS_DEBUG, "Bad PCIX MHz - Reset\n");
228 printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
229 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
231 printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
233 data = pci_read_config32(dev, 0x48);
236 printk(BIOS_DEBUG, "Bad Hot Swap start - Reset\n");
241 dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3));
242 pci_write_config8(dev, 0x41, 0xf1);
244 dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
245 htic = pci_read_config32(dev, HT_INIT_CONTROL);
246 htic &= ~HTIC_BIOSR_Detect;
247 pci_write_config32(dev, HT_INIT_CONTROL, htic);
251 printk(BIOS_DEBUG, "OK 133MHz & Hot Swap is off\n");
255 unsigned long write_smp_table(unsigned long addr)
260 v = smp_write_floating_table(addr, 0);
261 return (unsigned long)smp_write_config_table(v);