1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/x86/lapic.h>
11 #define HT_INIT_CONTROL 0x6c
12 #define HTIC_BIOSR_Detect (1<<5)
14 /* If we assume a symmetric processor configuration we can
15 * get all of the information we need to write the processor
16 * entry from the bootstrap processor.
17 * Plus I don't think linux really even cares.
18 * Having the proper apicid's in the table so the non-bootstrap
19 * processors can be woken up should be enough. Linux-2.6.11 work-around.
21 static void smp_write_processors_inorder(struct mp_config_table *mc)
25 unsigned apic_version;
26 unsigned cpu_features;
27 unsigned cpu_feature_flags;
28 struct cpuid_result result;
31 boot_apic_id = lapicid();
32 apic_version = lapic_read(LAPIC_LVR) & 0xff;
34 cpu_features = result.eax;
35 cpu_feature_flags = result.edx;
36 /* order the output of the cpus to fix a bug in kernel 6 11 */
37 for(order_id = 0;order_id <256; order_id++) {
38 for(cpu = all_devices; cpu; cpu = cpu->next) {
39 unsigned long cpu_flag;
40 if ((cpu->path.type != DEVICE_PATH_APIC) ||
41 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
48 cpu_flag = MPC_CPU_ENABLED;
49 if (boot_apic_id == cpu->path.apic.apic_id) {
50 cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
52 if(cpu->path.apic.apic_id == order_id) {
53 smp_write_processor(mc,
54 cpu->path.apic.apic_id, apic_version,
55 cpu_flag, cpu_features, cpu_feature_flags);
62 static unsigned node_link_to_bus(unsigned node, unsigned link)
67 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
71 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
76 config_map = pci_read_config32(dev, reg);
77 if ((config_map & 3) != 3) {
80 dst_node = (config_map >> 4) & 7;
81 dst_link = (config_map >> 8) & 3;
82 bus_base = (config_map >> 16) & 0xff;
84 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
85 dst_node, dst_link, bus_base,
88 if ((dst_node == node) && (dst_link == link))
96 static unsigned max_apicid(void)
101 for(dev = all_devices; dev; dev = dev->next) {
102 if (dev->path.type != DEVICE_PATH_APIC)
104 if (dev->path.apic.apic_id > max) {
105 max = dev->path.apic.apic_id;
111 static void *smp_write_config_table(void *v)
113 struct mp_config_table *mc;
115 unsigned char bus_chain_0;
116 unsigned char bus_8131_1;
117 unsigned char bus_8131_2;
118 unsigned char bus_8111_1;
119 unsigned apicid_base;
120 unsigned apicid_8111;
121 unsigned apicid_8131_1;
122 unsigned apicid_8131_2;
124 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
126 mptable_init(mc, LAPIC_ADDR);
128 smp_write_processors_inorder(mc);
130 apicid_base = max_apicid() + 1;
131 apicid_8111 = apicid_base;
132 apicid_8131_1 = apicid_base + 1;
133 apicid_8131_2 = apicid_base + 2;
138 bus_chain_0 = node_link_to_bus(0, 0);
139 if (bus_chain_0 == 0xff) {
140 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
145 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
147 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
150 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
154 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
156 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
159 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
163 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
165 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
168 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
173 mptable_write_buses(mc, NULL, &bus_isa);
175 /* IOAPIC handling */
176 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
179 struct resource *res;
181 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
183 res = find_resource(dev, PCI_BASE_ADDRESS_0);
185 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
189 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1));
191 res = find_resource(dev, PCI_BASE_ADDRESS_0);
193 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
198 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
200 /* Standard local interrupt assignments */
201 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
202 bus_isa, 0x00, MP_APIC_ALL, 0x00);
203 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
204 bus_isa, 0x00, MP_APIC_ALL, 0x01);
206 /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13);
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11);
214 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11);
215 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12);
216 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13);
217 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10);
220 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12);
221 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13);
222 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10);
223 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11);
226 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11);
227 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12);
228 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13);
229 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10);
232 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12);
233 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13);
234 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10);
235 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11);
238 // FIXME get the irqs right, it's just hacked to work for now
239 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11);
240 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12);
241 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13);
242 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10);
245 // FIXME get the irqs right, it's just hacked to work for now
246 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10);
247 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11);
248 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12);
249 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13);
251 /* There is no extension information... */
253 /* Compute the checksums */
254 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
255 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
256 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
257 mc, smp_next_mpe_entry(mc));
258 return smp_next_mpe_entry(mc);
261 static void reboot_if_hotswap(void)
263 /* Hack patch work around for hot swap enable 33mhz problem */
269 unsigned bus_chain_0 = node_link_to_bus(0, 0);
272 printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
273 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
275 printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
277 data = pci_read_config32(dev, 0xa0);
278 if(!(((data>>16)&0x03)==0x03)) {
280 printk(BIOS_DEBUG, "Bad PCIX MHz - Reset\n");
283 printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
284 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
286 printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
288 data = pci_read_config32(dev, 0x48);
291 printk(BIOS_DEBUG, "Bad Hot Swap start - Reset\n");
296 dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3));
297 pci_write_config8(dev, 0x41, 0xf1);
299 dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
300 htic = pci_read_config32(dev, HT_INIT_CONTROL);
301 htic &= ~HTIC_BIOSR_Detect;
302 pci_write_config32(dev, HT_INIT_CONTROL, htic);
306 printk(BIOS_DEBUG, "OK 133MHz & Hot Swap is off\n");
310 unsigned long write_smp_table(unsigned long addr)
315 v = smp_write_floating_table(addr);
316 return (unsigned long)smp_write_config_table(v);