1 #include <arch/pirq_routing.h>
2 #include <device/pci.h>
4 #define IRQ_ROUTER_BUS 1
5 #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
6 #define IRQ_ROUTER_VENDOR 0x1022
7 #define IRQ_ROUTER_DEVICE 0x746b
9 #define AVAILABLE_IRQS 0xdef8
10 #define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
11 { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
12 {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
14 /* Each IRQ_SLOT entry consists of:
15 * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
18 const struct irq_routing_table intel_irq_routing_table = {
19 PIRQ_SIGNATURE, /* u32 signature */
20 PIRQ_VERSION, /* u16 version */
21 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
22 IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
23 IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
24 0x00, /* IRQs devoted exclusively to PCI usage */
25 IRQ_ROUTER_VENDOR, /* Vendor */
26 IRQ_ROUTER_DEVICE, /* Device */
27 0x00, /* Crap (miniport) */
28 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
29 0xb0, /* u8 checksum , mod 256 checksum must give zero */
30 { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
32 IRQ_SLOT(1, 3,1,0, 2,3,4,1 ),
33 IRQ_SLOT(2, 3,2,0, 3,4,1,2 ),
34 IRQ_SLOT(3, 2,1,0, 2,3,4,1 ),
35 IRQ_SLOT(4, 2,2,0, 3,4,1,2 ),
36 IRQ_SLOT(5, 4,5,0, 2,3,4,1 ),
37 IRQ_SLOT(6, 4,4,0, 1,2,3,4 ),
39 IRQ_SLOT(0, 2,3,0, 4,0,0,0 ),
40 IRQ_SLOT(0, 2,4,0, 4,0,0,0 ),
41 /* Let Linux know about bus 1 */
42 IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
45 unsigned long write_pirq_routing_table(unsigned long addr)
47 return copy_pirq_routing_table(addr);