3 #include <device/pci_def.h>
4 #include <device/pci_ids.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include "pc80/mc146818rtc_early.c"
9 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
10 #include "northbridge/amd/amdk8/early_ht.c"
11 #include "cpu/x86/lapic/boot_cpu.c"
12 #include "northbridge/amd/amdk8/reset_test.c"
14 static unsigned long main(unsigned long bist)
18 /* Make cerain my local apic is useable */
21 nodeid = lapicid() & 0xf;
23 /* Is this a cpu only reset? */
24 if (cpu_init_detected(nodeid)) {
25 if (last_boot_normal()) {
31 /* Is this a secondary cpu? */
33 if (last_boot_normal()) {
41 /* Nothing special needs to be done to find bus 0 */
42 /* Allow the HT devices to be found */
48 /* Is this a deliberate reset by the bios */
49 if (bios_reset_detected() && last_boot_normal()) {
52 /* This is the primary cpu how should I boot? */
53 else if (do_normal_boot()) {
60 asm volatile ("jmp __normal_image"
62 : "a" (bist) /* inputs */
66 asm volatile ("jmp __cpu_reset"
68 : "a"(bist) /* inputs */