src/mainboard/arima/hdama/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <device/pnp.h>
   7 #include <arch/romcc_io.h>
   8 #include "pc80/serial.c"
   9 #include "arch/i386/lib/console.c"
  10 #include "ram/ramtest.c"
  11 #include "northbridge/amd/amdk8/early_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/k8/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/p6/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "debug.c"
  19
  20 static void memreset_setup(const struct mem_controller *ctrl)
  21 {
  22         /* Set the memreset low */
  23         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  24         /* Ensure the BIOS has control of the memory lines */
  25         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  26 }
  27
  28 static void memreset(const struct mem_controller *ctrl)
  29 {
  30         udelay(800);
  31         /* Set memreset_high */
  32         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  33         udelay(50);
  34 }
  35
  36 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  37 {
  38         /* Routing Table Node i
  39          *
  40          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  41          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  42          *
  43          * [ 0: 3] Request Route
  44          *     [0] Route to this node
  45          *     [1] Route to Link 0
  46          *     [2] Route to Link 1
  47          *     [3] Route to Link 2
  48          * [11: 8] Response Route
  49          *     [0] Route to this node
  50          *     [1] Route to Link 0
  51          *     [2] Route to Link 1
  52          *     [3] Route to Link 2
  53          * [19:16] Broadcast route
  54          *     [0] Route to this node
  55          *     [1] Route to Link 0
  56          *     [2] Route to Link 1
  57          *     [3] Route to Link 2
  58          */
  59
  60         uint32_t ret=0x00010101; /* default row entry */
  61
  62         static const unsigned int rows_2p[2][2] = {
  63                 { 0x00050101, 0x00010404 },
  64                 { 0x00010404, 0x00050101 }
  65         };
  66
  67         if(maxnodes>2) {
  68                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  69                 maxnodes=2;
  70         }
  71
  72
  73         if (!(node>=maxnodes || row>=maxnodes)) {
  74                 ret=rows_2p[node][row];
  75         }
  76
  77         return ret;
  78 }
  79
  80 #include "northbridge/amd/amdk8/cpu_ldtstop.c"
  81 #include "southbridge/amd/amd8111/amd8111_ldtstop.c"
  82
  83 #include "northbridge/amd/amdk8/raminit.c"
  84 #include "northbridge/amd/amdk8/coherent_ht.c"
  85 #include "sdram/generic_sdram.c"
  86
  87 static void enable_lapic(void)
  88 {
  89
  90         msr_t msr;
  91         msr = rdmsr(0x1b);
  92         msr.hi &= 0xffffff00;
  93         msr.lo &= 0x000007ff;
  94         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
  95         wrmsr(0x1b, msr);
  96 }
  97
  98 static void stop_this_cpu(void)
  99 {
 100         unsigned apicid;
 101         apicid = apic_read(APIC_ID) >> 24;
 102
 103         /* Send an APIC INIT to myself */
 104         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 105         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 106         /* Wait for the ipi send to finish */
 107         apic_wait_icr_idle();
 108
 109         /* Deassert the APIC INIT */
 110         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 111         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 112         /* Wait for the ipi send to finish */
 113         apic_wait_icr_idle();
 114
 115         /* If I haven't halted spin forever */
 116         for(;;) {
 117                 hlt();
 118         }
 119 }
 120
 121 #define PC87360_FDC  0x00
 122 #define PC87360_PP   0x01
 123 #define PC87360_SP2  0x02
 124 #define PC87360_SP1  0x03
 125 #define PC87360_SWC  0x04
 126 #define PC87360_KBCM 0x05
 127 #define PC87360_KBCK 0x06
 128 #define PC87360_GPIO 0x07
 129 #define PC87360_ACB  0x08
 130 #define PC87360_FSCM 0x09
 131 #define PC87360_WDT  0x0A
 132
 133 static void pc87360_enable_serial(void)
 134 {
 135         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 136         pnp_set_enable(SIO_BASE, 1);
 137         pnp_set_iobase0(SIO_BASE, 0x3f8);
 138 }
 139
 140 static void main(void)
 141 {
 142         /*
 143          * GPIO28 of 8111 will control H0_MEMRESET_L
 144          * GPIO29 of 8111 will control H1_MEMRESET_L
 145          */
 146
 147         static const struct mem_controller cpu0 = {
 148                 .f0 = PCI_DEV(0, 0x18, 0),
 149                 .f1 = PCI_DEV(0, 0x18, 1),
 150                 .f2 = PCI_DEV(0, 0x18, 2),
 151                 .f3 = PCI_DEV(0, 0x18, 3),
 152                 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 153                 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 154         };
 155         static const struct mem_controller cpu1 = {
 156                 .f0 = PCI_DEV(0, 0x19, 0),
 157                 .f1 = PCI_DEV(0, 0x19, 1),
 158                 .f2 = PCI_DEV(0, 0x19, 2),
 159                 .f3 = PCI_DEV(0, 0x19, 3),
 160                 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 161                 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 162         };
 163         if (cpu_init_detected()) {
 164                 asm("jmp __cpu_reset");
 165         }
 166         pc87360_enable_serial();
 167         uart_init();
 168         console_init();
 169         enable_lapic();
 170         if (!boot_cpu()) {
 171                 stop_this_cpu();
 172         }
 173         init_timer();
 174         setup_default_resource_map();
 175         setup_coherent_ht_domain();
 176         enumerate_ht_chain(0);
 177         distinguish_cpu_resets();
 178
 179 #if 1
 180         print_pci_devices();
 181 #endif
 182         enable_smbus();
 183 #if 0
 184         dump_spd_registers(&cpu0);
 185 #endif
 186         sdram_initialize(&cpu0);
 187
 188 #if 1
 189         dump_pci_devices();
 190 #endif
 191 #if 0
 192         dump_pci_device(PCI_DEV(0, 0x18, 2));
 193 #endif
 194
 195         /* Check all of memory */
 196 #if 0
 197         msr_t msr;
 198         msr = rdmsr(TOP_MEM);
 199         print_debug("TOP_MEM: ");
 200         print_debug_hex32(msr.hi);
 201         print_debug_hex32(msr.lo);
 202         print_debug("\r\n");
 203 #endif
 204 #if 0
 205         ram_check(0x00000000, msr.lo);
 206 #else
 207         /* Check 16MB of memory */
 208         ram_check(0x00000000, 0x01000000);
 209 #endif
 210 }