2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=131072
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
53 depends "$(MAINBOARD)/failover.c ./romcc"
54 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
57 makerule ./failover.inc
58 depends "$(MAINBOARD)/failover.c ./romcc"
59 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
63 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
64 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
67 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
68 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
72 ## Build our 16 bit and 32 bit linuxBIOS entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
77 ldscript /cpu/x86/32bit/entry32.lds
80 ## Build our reset vector (This is where linuxBIOS is entered)
83 mainboardinit cpu/x86/16bit/reset16.inc
84 ldscript /cpu/x86/16bit/reset16.lds
86 mainboardinit cpu/x86/32bit/reset32.inc
87 ldscript /cpu/x86/32bit/reset32.lds
90 ### Should this be in the northbridge code?
91 mainboardinit arch/i386/lib/cpu_reset.inc
94 ## Include an id string (For safe flashing)
96 mainboardinit arch/i386/lib/id.inc
97 ldscript /arch/i386/lib/id.lds
100 ### This is the early phase of linuxBIOS startup
101 ### Things are delicate and we test to see if we should
102 ### failover to another image.
104 if USE_FALLBACK_IMAGE
105 ldscript /arch/i386/lib/failover.lds
106 mainboardinit ./failover.inc
110 ### O.k. We aren't just an intermediary anymore!
116 mainboardinit cpu/x86/fpu/enable_fpu.inc
117 mainboardinit cpu/x86/mmx/enable_mmx.inc
118 mainboardinit cpu/x86/sse/enable_sse.inc
119 mainboardinit ./auto.inc
120 mainboardinit cpu/x86/sse/disable_sse.inc
121 mainboardinit cpu/x86/mmx/disable_mmx.inc
124 ## Include the secondary Configuration files
129 # config for arima/hdama
130 chip northbridge/amd/amdk8/root_complex
131 device apic_cluster 0 on
132 chip cpu/amd/socket_940
136 device pci_domain 0 on
137 chip northbridge/amd/amdk8
138 device pci 18.0 on # northbridge
139 # devices on link 0, link 0 == LDT 0
140 chip southbridge/amd/amd8131
141 # the on/off keyword is mandatory
142 device pci 0.0 on # PCIX bridge
144 #chip drivers/generic/generic
150 #chip drivers/generic/generic
156 #chip drivers/generic/generic
165 #chip drivers/generic/generic
174 device pci 0.1 on end # IOAPIC
175 device pci 1.0 on # PCIX bridge
177 #chip drivers/generic/generic
186 #chip drivers/generic/generic
195 device pci 1.1 on end # IOAPIC
197 chip southbridge/amd/amd8111
198 # this "device pci 0.0" is the parent of the next one
201 device pci 0.0 on end # USB0
202 device pci 0.1 on end # USB1
203 device pci 0.2 off end # USB 2.0
204 device pci 1.0 off end # LAN
205 chip drivers/pci/onboard
206 device pci 6.0 on end # ATI Rage XL
207 register "rom_address" = "0xfff80000"
209 ## PCI Slot 5 (correct?)
210 #chip drivers/generic/generic
218 ## PCI Slot 6 (correct?)
219 #chip drivers/generic/generic
231 chip superio/nsc/pc87360
232 device pnp 2e.0 off # Floppy
237 device pnp 2e.1 off # Parallel Port
241 device pnp 2e.2 off # Com 2
245 device pnp 2e.3 on # Com 1
249 device pnp 2e.4 off end # SWC
250 device pnp 2e.5 off end # Mouse
251 device pnp 2e.6 on # Keyboard
256 device pnp 2e.7 off end # GPIO
257 device pnp 2e.8 off end # ACB
258 device pnp 2e.9 off end # FSCM
259 device pnp 2e.a off end # WDT
262 device pci 1.1 on end # IDE
263 device pci 1.2 on end # SMBus 2.0
264 device pci 1.3 on # System Management
265 chip drivers/generic/generic
266 #phillips pca9545 smbus mux
268 # analog_devices adm1026
269 chip drivers/generic/generic
277 chip drivers/generic/generic #dimm 0-0-0
280 chip drivers/generic/generic #dimm 0-0-1
283 chip drivers/generic/generic #dimm 0-1-0
286 chip drivers/generic/generic #dimm 0-1-1
289 chip drivers/generic/generic #dimm 1-0-0
292 chip drivers/generic/generic #dimm 1-0-1
295 chip drivers/generic/generic #dimm 1-1-0
298 chip drivers/generic/generic #dimm 1-1-1
302 device pci 1.5 off end # AC97 Audio
303 device pci 1.6 on end # AC97 Modem
304 register "ide0_enable" = "1"
305 register "ide1_enable" = "1"
307 end # device pci 18.0
309 device pci 18.0 on end # LDT1
310 device pci 18.0 on end # LDT2
311 device pci 18.1 on end
312 device pci 18.2 on end
313 device pci 18.3 on end
314 end # chip northbridge/amd/amdk8
315 chip northbridge/amd/amdk8
316 device pci 19.0 on end
317 device pci 19.0 on end
318 device pci 19.0 on end
319 device pci 19.1 on end
320 device pci 19.2 on end
321 device pci 19.3 on end