2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
27 #include <cpu/amd/amdfam14.h>
28 #include <SBPLATFORM.h>
30 extern u8 bus_sb800[2];
32 extern u32 apicid_sb800;
34 extern u32 bus_type[256];
35 extern u32 sbdn_sb800;
38 [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
39 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
40 [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
41 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
43 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
47 static void *smp_write_config_table(void *v)
49 struct mp_config_table *mc;
52 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
54 mptable_init(mc, LAPIC_ADDR);
55 memcpy(mc->mpc_oem, "AMD ", 8);
57 smp_write_processors(mc);
61 mptable_write_buses(mc, NULL, &bus_isa);
63 /* I/O APICs: APIC ID Version State Address */
68 ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
70 smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
72 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
73 outb(byte | 0x80, 0xC00);
74 outb(intr_data[byte], 0xC01);
77 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
78 #define IO_LOCAL_INT(type, intr, apicid, pin) \
79 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
81 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
83 /* PCI interrupts are level triggered, and are
84 * associated with a specific bus/device/function tuple.
86 #if CONFIG_GENERATE_ACPI_TABLES == 0
87 #define PCI_INT(bus, dev, fn, pin) \
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
90 #define PCI_INT(bus, dev, fn, pin)
93 //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
94 PCI_INT(0x0, 0x14, 0x0, 0x10);
96 PCI_INT(0x0, 0x14, 0x2, 0x12);
98 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
99 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
100 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
101 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
102 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
103 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
106 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
108 /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
110 /* on board NIC & Slot PCIE. */
114 PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
115 PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
116 PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
117 PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
120 PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
121 PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
122 PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
123 PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
126 PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
127 PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
128 PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
129 PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
131 PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
132 PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
133 PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
136 PCI_INT(0x0, 0x15, 0x0, 0x10);
138 PCI_INT(0x0, 0x15, 0x1, 0x11);
140 PCI_INT(0x0, 0x15, 0x2, 0x12);
142 PCI_INT(0x0, 0x15, 0x3, 0x13);
144 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
145 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
146 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
147 /* There is no extension information... */
149 /* Compute the checksums */
150 return mptable_finalize(mc);
153 unsigned long write_smp_table(unsigned long addr)
156 v = smp_write_floating_table(addr, 0);
157 return (unsigned long)smp_write_config_table(v);