2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
28 #include <cpu/x86/lapic.h>
29 #include <cpu/amd/amdfam12.h>
30 #include "SbPlatform.h"
32 //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
33 #define IO_APIC_ID CONFIG_MAX_CPUS
34 extern u8 bus_sb900[2];
37 extern u32 bus_type[256];
38 extern u32 sbdn_sb900;
42 0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
43 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
44 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
45 0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
46 0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
50 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
51 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
52 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
53 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
54 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
58 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
60 mc->mpc_length += length;
61 mc->mpc_entry_count++;
63 static void my_smp_write_bus(struct mp_config_table *mc,
64 unsigned char id, const char *bustype)
66 struct mpc_config_bus *mpc;
67 mpc = smp_next_mpc_entry(mc);
68 memset(mpc, '\0', sizeof(*mpc));
69 mpc->mpc_type = MP_BUS;
71 memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
72 smp_add_mpc_entry(mc, sizeof(*mpc));
74 static void *smp_write_config_table(void *v)
76 struct mp_config_table *mc;
79 unsigned apic_version;
80 unsigned cpu_features;
81 unsigned cpu_feature_flags;
82 struct cpuid_result result;
83 unsigned long cpu_flag;
85 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
87 mptable_init(mc, LAPIC_ADDR);
88 memcpy(mc->mpc_oem, "AMD ", 8);
90 /*Inagua used dure core cpu with one die */
91 boot_apic_id = lapicid();
92 apic_version = lapic_read(LAPIC_LVR) & 0xff;
94 cpu_features = result.eax;
95 cpu_feature_flags = result.edx;
96 cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
97 smp_write_processor(mc,
99 cpu_flag, cpu_features, cpu_feature_flags
102 cpu_flag = MPC_CPU_ENABLED;
103 smp_write_processor(mc,
105 cpu_flag, cpu_features, cpu_feature_flags
110 //mptable_write_buses(mc, NULL, &bus_isa);
111 my_smp_write_bus(mc, 0, "PCI ");
112 my_smp_write_bus(mc, 1, "PCI ");
114 my_smp_write_bus(mc, bus_isa, "ISA ");
116 /* I/O APICs: APIC ID Version State Address */
121 ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
123 /* Set IO APIC ID onto IO_APIC_ID */
124 write32 (dword, 0x00);
125 write32 (dword + 0x10, IO_APIC_ID << 24);
126 apicid_sb900 = IO_APIC_ID;
127 smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
129 /* PIC IRQ routine */
130 for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
132 outb(picr_data[byte], 0xC01);
135 /* APIC IRQ routine */
136 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
137 outb(byte | 0x80, 0xC00);
138 outb(intr_data[byte], 0xC01);
141 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
142 #define IO_LOCAL_INT(type, intr, apicid, pin) \
143 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
145 //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
146 /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1);
149 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd);
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf);
164 /* PCI interrupts are level triggered, and are
165 * associated with a specific bus/device/function tuple.
167 #if CONFIG_GENERATE_ACPI_TABLES == 0
168 #define PCI_INT(bus, dev, int_sign, pin) \
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
171 #define PCI_INT(bus, dev, fn, pin)
175 PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
176 PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
179 PCI_INT(0x0, 0x14, 0x0, 0x10);
182 PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
185 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
186 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
187 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
188 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
189 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
190 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
191 PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
194 PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
195 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
198 /* on board NIC & Slot PCIE. */
202 PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
203 PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
204 PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
205 PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
208 PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
209 PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
210 PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
211 PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
214 PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
215 PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
216 PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
217 PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
219 PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12);
220 PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13);
221 PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14);
224 PCI_INT(0x0, 0x06, 0x0, 0x13);
227 PCI_INT(0x0, 0x15, 0x0, 0x10);
229 PCI_INT(0x0, 0x15, 0x1, 0x11);
231 PCI_INT(0x0, 0x15, 0x2, 0x12);
233 PCI_INT(0x0, 0x15, 0x3, 0x13);
235 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
236 IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
237 IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
238 /* There is no extension information... */
240 /* Compute the checksums */
241 return mptable_finalize(mc);
244 unsigned long write_smp_table(unsigned long addr)
247 v = smp_write_floating_table(addr, 0);
248 return (unsigned long)smp_write_config_table(v);