2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "heapManager.h"
24 #include "PlatformGnbPcieComplex.h"
27 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
29 /*---------------------------------------------------------------------------------------*/
31 * OemCustomizeInitEarly
34 * This is the stub function will call the host environment through the binary block
35 * interface (call-out port) to provide a user hook opportunity
38 * @param[in] **PeiServices
39 * @param[in] *InitEarly
44 /*---------------------------------------------------------------------------------------*/
46 OemCustomizeInitEarly (
47 IN OUT AMD_EARLY_PARAMS *InitEarly
51 VOID *BrazosPcieComplexListPtr;
52 VOID *BrazosPciePortPtr;
53 VOID *BrazosPcieDdiPtr;
55 ALLOCATE_HEAP_PARAMS AllocHeapParams;
57 PCIe_PORT_DESCRIPTOR PortList [] = {
58 // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
60 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
61 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
62 PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
65 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
67 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
68 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
69 PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
71 // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
73 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
74 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
75 PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
77 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
80 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
81 PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
84 // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
86 DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
87 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
88 PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
92 PCIe_DDI_DESCRIPTOR DdiList [] = {
93 /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
96 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
97 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
99 /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
101 DESCRIPTOR_TERMINATE_LIST,
102 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
103 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1)
107 PCIe_COMPLEX_DESCRIPTOR Brazos = {
108 DESCRIPTOR_TERMINATE_LIST,
114 // GNB PCIe topology Porting
117 // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
119 AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
120 sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
121 sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
123 AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
124 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
125 Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
126 if ( Status!= AGESA_SUCCESS) {
127 // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
132 BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
134 AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
135 BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
137 AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
138 BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
140 LibAmdMemFill (BrazosPcieComplexListPtr,
142 sizeof (PCIe_COMPLEX_DESCRIPTOR),
143 &InitEarly->StdHeader);
145 LibAmdMemFill (BrazosPciePortPtr,
147 sizeof (PCIe_PORT_DESCRIPTOR) * 5,
148 &InitEarly->StdHeader);
150 LibAmdMemFill (BrazosPcieDdiPtr,
152 sizeof (PCIe_DDI_DESCRIPTOR) * 2,
153 &InitEarly->StdHeader);
155 LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
156 LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
157 LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
160 ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
161 ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
163 InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
164 InitEarly->GnbConfig.PsppPolicy = 0;