2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /** This file defines the SPD addresses for the mainboard. */
24 static const u8 spd_addr[] = {
26 RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
27 #if CONFIG_MAX_PHYSICAL_CPUS > 1
29 RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
31 #if CONFIG_MAX_PHYSICAL_CPUS > 2
33 RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
35 RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
37 #if CONFIG_MAX_PHYSICAL_CPUS > 4
38 RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
39 RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
41 #if CONFIG_MAX_PHYSICAL_CPUS > 6
42 RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
43 RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
45 #if CONFIG_MAX_PHYSICAL_CPUS > 8
46 RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
47 RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
48 RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
49 RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
51 #if CONFIG_MAX_PHYSICAL_CPUS > 12
52 RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
53 RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
54 RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
55 RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
57 #if CONFIG_MAX_PHYSICAL_CPUS > 16
58 RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
59 RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
60 RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
61 RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
63 #if CONFIG_MAX_PHYSICAL_CPUS > 20
64 RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
65 RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
66 RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
67 RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
69 #if CONFIG_MAX_PHYSICAL_CPUS > 24
70 RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
71 RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
72 RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
73 RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
74 RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
75 RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
76 RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
77 RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
79 #if CONFIG_MAX_PHYSICAL_CPUS > 32
80 RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
81 RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
82 RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
83 RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
84 RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
85 RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
86 RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
87 RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
88 RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
89 RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
90 RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
91 RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
92 RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
93 RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
94 RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
95 RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
97 #if CONFIG_MAX_PHYSICAL_CPUS > 48
98 RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
99 RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
100 RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
101 RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
102 RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
103 RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
104 RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
105 RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
106 RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
107 RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
108 RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
109 RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
110 RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
111 RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
112 RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
113 RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,