2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #define SYSTEM_TYPE 0 /* SERVER */
25 //#define SYSTEM_TYPE 1 /* DESKTOP */
26 //#define SYSTEM_TYPE 2 /* MOBILE */
29 #define RAMINIT_SYSINFO 1
30 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
32 #define SET_NB_CFG_54 1
35 #define QRANK_DIMM_SUPPORT 1
37 //used by incoherent_ht
38 #define FAM10_SCAN_PCI_BUS 0
39 #define FAM10_ALLOCATE_IO_RANGE 0
41 //used by init_cpus and fidvid
42 #define FAM10_SET_FIDVID 1
43 #define FAM10_SET_FIDVID_CORE_RANGE 0
47 #include <device/pci_def.h>
48 #include <device/pci_ids.h>
50 #include <device/pnp_def.h>
51 #include <arch/romcc_io.h>
52 #include <cpu/x86/lapic.h>
53 #include "option_table.h"
54 #include "pc80/mc146818rtc_early.c"
56 /* FIXME: Use console.c post_code function */
57 static void post_code(u8 value) {
61 #include "arch/i386/lib/console.c"
62 #include "pc80/serial.c"
63 #include "lib/ramtest.c"
64 #include <cpu/amd/model_10xxx_rev.h>
65 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
66 #include "northbridge/amd/amdfam10/raminit.h"
67 #include "northbridge/amd/amdfam10/amdfam10.h"
69 #include "cpu/x86/lapic/boot_cpu.c"
70 #include "northbridge/amd/amdfam10/reset_test.c"
72 #include <console/loglevel.h>
74 void die(const char *msg);
75 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
76 #define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
78 #include "cpu/x86/bist.h"
81 #include "northbridge/amd/amdfam10/debug.c"
82 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
83 #include "cpu/amd/mtrr/amd_earlymtrr.c"
84 #include "northbridge/amd/amdfam10/setup_resource_map.c"
86 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
87 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
89 static void memreset_setup(void)
91 //GPIO on amd8111 to enable MEMRST ????
92 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
93 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
97 static void memreset(int controllers, const struct mem_controller *ctrl)
102 static void activate_spd_rom(const struct mem_controller *ctrl)
104 #define SMBUS_HUB 0x18
106 u8 device = ctrl->spd_switch_addr;
108 printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
110 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
113 ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
114 } while ((ret!=0) && (i-->0));
115 smbus_write_byte(SMBUS_HUB, 0x03, 0);
119 static int spd_read_byte(u32 device, u32 address)
122 result = smbus_read_byte(device, address);
126 #include "northbridge/amd/amdfam10/amdfam10.h"
127 #include "northbridge/amd/amdht/ht_wrapper.c"
129 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
130 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
131 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
133 #include "resourcemap.c"
134 #include "cpu/amd/quadcore/quadcore.c"
135 #include "cpu/amd/car/copy_and_run.c"
136 #include "cpu/amd/car/post_cache_as_ram.c"
137 #include "cpu/amd/model_10xxx/init_cpus.c"
138 #include "cpu/amd/model_10xxx/fidvid.c"
141 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
142 #include "northbridge/amd/amdfam10/early_ht.c"
144 #include "spd_addr.h"
145 #include "cpu/amd/microcode/microcode.c"
146 #include "cpu/amd/model_10xxx/update_microcode.c"
148 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
151 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
156 if (!cpu_init_detectedx && boot_cpu()) {
157 /* Nothing special needs to be done to find bus 0 */
158 /* Allow the HT devices to be found */
159 /* mov bsp to bus 0xff when > 8 nodes */
160 set_bsp_node_CHtExtNodeCfgEn();
161 enumerate_ht_chain();
163 /* Setup the rom access for 4M */
164 amd8111_enable_rom();
170 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
171 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
176 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
179 printk(BIOS_DEBUG, "\n");
181 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
183 /* Halt if there was a built in self test failure */
184 report_bist_failure(bist);
188 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
189 printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
190 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
191 printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
193 /* Setup sysinfo defaults */
194 set_sysinfo_in_ram(0);
196 update_microcode(val);
202 amd_ht_init(sysinfo);
205 /* Setup nodes PCI space and start core 0 AP init. */
206 finalize_node_setup(sysinfo);
208 /* Setup any mainboard PCI settings etc. */
209 setup_mb_resource_map();
212 /* wait for all the APs core0 started by finalize_node_setup. */
213 /* FIXME: A bunch of cores are going to start output to serial at once.
214 It would be nice to fixup prink spinlocks for ROM XIP mode.
215 I think it could be done by putting the spinlock flag in the cache
216 of the BSP located right after sysinfo.
218 wait_all_core0_started();
220 #if CONFIG_LOGICAL_CPUS==1
221 /* Core0 on each node is configured. Now setup any additional cores. */
222 printk(BIOS_DEBUG, "start_other_cores()\n");
225 wait_all_other_cores_started(bsp_apicid);
230 #if FAM10_SET_FIDVID == 1
231 msr = rdmsr(0xc0010071);
232 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
234 /* FIXME: The sb fid change may survive the warm reset and only
235 need to be done once.*/
236 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
240 if (!warm_reset_detect(0)) { // BSP is node 0
241 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
243 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
248 /* show final fid and vid */
249 msr=rdmsr(0xc0010071);
250 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
254 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
255 if (!warm_reset_detect(0)) {
256 print_info("...WARM RESET...\n\n\n");
257 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
258 die("After soft_reset_x - shouldn't see this message!!!\n");
264 /* FIXME: Move this to chipset init.
265 enable cf9 for hard reset */
266 print_debug("enable_cf9_x()\n");
267 enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
270 /* It's the time to set ctrl in sysinfo now; */
271 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
272 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
276 printk(BIOS_DEBUG, "enable_smbus()\n");
284 // die("Die Before MCT init.");
286 printk(BIOS_DEBUG, "raminit_amdmct()\n");
287 raminit_amdmct(sysinfo);
292 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
293 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
294 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
295 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
298 // ram_check(0x00200000, 0x00200000 + (640 * 1024));
299 // ram_check(0x40200000, 0x40200000 + (640 * 1024));
302 // die("After MCT init before CAR disabled.");
305 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
306 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
307 post_code(0x43); // Should never see this post code.