src/mainboard/amd/serengeti_cheetah_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <arch/ioapic.h>
  23 #include <device/pci.h>
  24 #include <string.h>
  25 #include <stdint.h>
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #include <cpu/amd/multicore.h>
  28 #endif
  29 #include <cpu/amd/amdfam10_sysconf.h>
  30 #include "mb_sysconf.h"
  31
  32 static void *smp_write_config_table(void *v)
  33 {
  34         int i, j, bus_isa;
  35         struct mp_config_table *mc;
  36         struct mb_sysconf_t *m;
  37
  38         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  39
  40         mptable_init(mc, LAPIC_ADDR);
  41
  42         smp_write_processors(mc);
  43
  44         get_bus_conf();
  45
  46         m = sysconf.mb;
  47
  48         mptable_write_buses(mc, NULL, &bus_isa);
  49
  50         /*I/O APICs:    APIC ID Version State   Address*/
  51         smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
  52         {
  53                 device_t dev;
  54                 struct resource *res;
  55                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  56                 if (dev) {
  57                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  58                         if (res) {
  59                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  60                         }
  61                 }
  62                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  63                 if (dev) {
  64                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  65                         if (res) {
  66                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  67                         }
  68                 }
  69
  70                 j = 0;
  71
  72                 for(i=1; i< sysconf.hc_possible_num; i++) {
  73                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
  74
  75                         switch(sysconf.hcid[i]) {
  76                         case 1:
  77                         case 3:
  78                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
  79                                 if (dev) {
  80                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  81                                         if (res) {
  82                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
  83                                         }
  84                                 }
  85                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
  86                                 if (dev) {
  87                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  88                                         if (res) {
  89                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
  90                                         }
  91                                 }
  92                                 break;
  93                         }
  94                         j++;
  95                 }
  96
  97         }
  98
  99         mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
 100
 101         /* I/O Ints:    Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 102 //??? What
 103         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 104
 105         // Onboard AMD USB
 106          smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 107
 108         //Slot 3  PCI 32
 109         for(i=0;i<4;i++) {
 110                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 111         }
 112
 113
 114         // Slot 4 PCI 32
 115         for(i=0;i<4;i++) {
 116                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 117         }
 118
 119
 120         // Slot 1 PCI-X 133/100/66
 121         for(i=0;i<4;i++) {
 122                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 123         }
 124
 125
 126         //Slot 2 PCI-X 133/100/66
 127         for(i=0;i<4;i++) {
 128                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 129         }
 130
 131         j = 0;
 132
 133         for(i=1; i< sysconf.hc_possible_num; i++) {
 134                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 135                 int ii;
 136                 int jj;
 137                 device_t dev;
 138                 struct resource *res;
 139                 switch(sysconf.hcid[i]) {
 140                 case 1:
 141                 case 3:
 142                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 143                         if (dev) {
 144                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 145                                 if (res) {
 146                                         for(jj=0; jj<4; jj++) {
 147                                                 //Slot 1 PCI-X 133/100/66
 148                                                 for(ii=0;ii<4;ii++) {
 149                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
 150                                                 }
 151                                         }
 152                                 }
 153                         }
 154
 155                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 156                         if (dev) {
 157                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 158                                 if (res) {
 159                                         for(jj=0; jj<4; jj++) {
 160                                                 //Slot 2 PCI-X 133/100/66
 161                                                 for(ii=0;ii<4;ii++) {
 162                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
 163                                                 }
 164                                         }
 165                                 }
 166                         }
 167
 168                         break;
 169                 case 2:
 170
 171                 //  Slot AGP
 172                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 173                         break;
 174                 }
 175
 176                 j++;
 177          }
 178
 179
 180
 181         /* Local Ints:  Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 182         mptable_lintsrc(mc, bus_isa);
 183         /* There is no extension information... */
 184
 185         /* Compute the checksums */
 186         return mptable_finalize(mc);
 187 }
 188
 189 unsigned long write_smp_table(unsigned long addr)
 190 {
 191         void *v;
 192         v = smp_write_floating_table(addr, 0);
 193         return (unsigned long)smp_write_config_table(v);
 194 }