src/mainboard/amd/serengeti_cheetah_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <arch/ioapic.h>
  23 #include <device/pci.h>
  24 #include <string.h>
  25 #include <stdint.h>
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #include <cpu/amd/multicore.h>
  28 #endif
  29
  30 #include <cpu/amd/amdfam10_sysconf.h>
  31 #include "mb_sysconf.h"
  32
  33
  34
  35 static void *smp_write_config_table(void *v)
  36 {
  37         static const char sig[4] = "PCMP";
  38         static const char oem[8] = "COREBOOT";
  39         static const char productid[12] = "SERENGETI    ";
  40         struct mp_config_table *mc;
  41
  42         int i;
  43         int j;
  44         struct mb_sysconf_t *m;
  45
  46         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  47         memset(mc, 0, sizeof(*mc));
  48
  49         memcpy(mc->mpc_signature, sig, sizeof(sig));
  50         mc->mpc_length = sizeof(*mc); /* initially just the header */
  51         mc->mpc_spec = 0x04;
  52         mc->mpc_checksum = 0; /* not yet computed */
  53         memcpy(mc->mpc_oem, oem, sizeof(oem));
  54         memcpy(mc->mpc_productid, productid, sizeof(productid));
  55         mc->mpc_oemptr = 0;
  56         mc->mpc_oemsize = 0;
  57         mc->mpc_entry_count = 0; /* No entries yet... */
  58         mc->mpc_lapic = LAPIC_ADDR;
  59         mc->mpe_length = 0;
  60         mc->mpe_checksum = 0;
  61         mc->reserved = 0;
  62
  63         smp_write_processors(mc);
  64
  65         get_bus_conf();
  66
  67         m = sysconf.mb;
  68
  69         /*Bus:  Bus ID  Type*/
  70         /* define bus and isa numbers */
  71         for(j= 0; j < 256 ; j++) {
  72                 if(m->bus_type[j])
  73                         smp_write_bus(mc, j, "PCI   ");
  74         }
  75         smp_write_bus(mc, m->bus_isa, "ISA   ");
  76
  77         /*I/O APICs:    APIC ID Version State   Address*/
  78         smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
  79         {
  80                 device_t dev;
  81                 struct resource *res;
  82                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  83                 if (dev) {
  84                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  85                         if (res) {
  86                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  87                         }
  88                 }
  89                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  90                 if (dev) {
  91                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  92                         if (res) {
  93                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  94                         }
  95                 }
  96
  97                 j = 0;
  98
  99                 for(i=1; i< sysconf.hc_possible_num; i++) {
 100                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
 101
 102                         switch(sysconf.hcid[i]) {
 103                         case 1:
 104                         case 3:
 105                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 106                                 if (dev) {
 107                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 108                                         if (res) {
 109                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
 110                                         }
 111                                 }
 112                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 113                                 if (dev) {
 114                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 115                                         if (res) {
 116                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
 117                                         }
 118                                 }
 119                                 break;
 120                         }
 121                         j++;
 122                 }
 123
 124         }
 125
 126         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
 127
 128         /* I/O Ints:    Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 129 //??? What
 130         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 131
 132         // Onboard AMD USB
 133          smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 134
 135         //Slot 3  PCI 32
 136         for(i=0;i<4;i++) {
 137                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 138         }
 139
 140
 141         // Slot 4 PCI 32
 142         for(i=0;i<4;i++) {
 143                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 144         }
 145
 146
 147         // Slot 1 PCI-X 133/100/66
 148         for(i=0;i<4;i++) {
 149                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 150         }
 151
 152
 153         //Slot 2 PCI-X 133/100/66
 154         for(i=0;i<4;i++) {
 155                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 156         }
 157
 158         j = 0;
 159
 160         for(i=1; i< sysconf.hc_possible_num; i++) {
 161                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 162                 int ii;
 163                 int jj;
 164                 device_t dev;
 165                 struct resource *res;
 166                 switch(sysconf.hcid[i]) {
 167                 case 1:
 168                 case 3:
 169                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 170                         if (dev) {
 171                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 172                                 if (res) {
 173                                         for(jj=0; jj<4; jj++) {
 174                                                 //Slot 1 PCI-X 133/100/66
 175                                                 for(ii=0;ii<4;ii++) {
 176                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
 177                                                 }
 178                                         }
 179                                 }
 180                         }
 181
 182                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 183                         if (dev) {
 184                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 185                                 if (res) {
 186                                         for(jj=0; jj<4; jj++) {
 187                                                 //Slot 2 PCI-X 133/100/66
 188                                                 for(ii=0;ii<4;ii++) {
 189                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
 190                                                 }
 191                                         }
 192                                 }
 193                         }
 194
 195                         break;
 196                 case 2:
 197
 198                 //  Slot AGP
 199                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 200                         break;
 201                 }
 202
 203                 j++;
 204          }
 205
 206
 207
 208         /* Local Ints:  Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 209         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 210         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 211         /* There is no extension information... */
 212
 213         /* Compute the checksums */
 214         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 215         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 216         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 217                 mc, smp_next_mpe_entry(mc));
 218         return smp_next_mpe_entry(mc);
 219 }
 220
 221 unsigned long write_smp_table(unsigned long addr)
 222 {
 223         void *v;
 224         v = smp_write_floating_table(addr);
 225         return (unsigned long)smp_write_config_table(v);
 226 }