src/mainboard/amd/serengeti_cheetah_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <arch/ioapic.h>
  23 #include <device/pci.h>
  24 #include <string.h>
  25 #include <stdint.h>
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #include <cpu/amd/multicore.h>
  28 #endif
  29 #include <cpu/amd/amdfam10_sysconf.h>
  30 #include "mb_sysconf.h"
  31
  32 static void *smp_write_config_table(void *v)
  33 {
  34         int i, j;
  35         struct mp_config_table *mc;
  36         struct mb_sysconf_t *m;
  37
  38         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  39
  40         mptable_init(mc, "SERENGETI   ", LAPIC_ADDR);
  41
  42         smp_write_processors(mc);
  43
  44         get_bus_conf();
  45
  46         m = sysconf.mb;
  47
  48         /*Bus:  Bus ID  Type*/
  49         /* define bus and isa numbers */
  50         for(j= 0; j < 256 ; j++) {
  51                 if(m->bus_type[j])
  52                         smp_write_bus(mc, j, "PCI   ");
  53         }
  54         smp_write_bus(mc, m->bus_isa, "ISA   ");
  55
  56         /*I/O APICs:    APIC ID Version State   Address*/
  57         smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
  58         {
  59                 device_t dev;
  60                 struct resource *res;
  61                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  62                 if (dev) {
  63                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  64                         if (res) {
  65                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  66                         }
  67                 }
  68                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  69                 if (dev) {
  70                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  71                         if (res) {
  72                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  73                         }
  74                 }
  75
  76                 j = 0;
  77
  78                 for(i=1; i< sysconf.hc_possible_num; i++) {
  79                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
  80
  81                         switch(sysconf.hcid[i]) {
  82                         case 1:
  83                         case 3:
  84                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
  85                                 if (dev) {
  86                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  87                                         if (res) {
  88                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
  89                                         }
  90                                 }
  91                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
  92                                 if (dev) {
  93                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  94                                         if (res) {
  95                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
  96                                         }
  97                                 }
  98                                 break;
  99                         }
 100                         j++;
 101                 }
 102
 103         }
 104
 105         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
 106
 107         /* I/O Ints:    Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 108 //??? What
 109         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 110
 111         // Onboard AMD USB
 112          smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 113
 114         //Slot 3  PCI 32
 115         for(i=0;i<4;i++) {
 116                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 117         }
 118
 119
 120         // Slot 4 PCI 32
 121         for(i=0;i<4;i++) {
 122                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 123         }
 124
 125
 126         // Slot 1 PCI-X 133/100/66
 127         for(i=0;i<4;i++) {
 128                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 129         }
 130
 131
 132         //Slot 2 PCI-X 133/100/66
 133         for(i=0;i<4;i++) {
 134                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 135         }
 136
 137         j = 0;
 138
 139         for(i=1; i< sysconf.hc_possible_num; i++) {
 140                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 141                 int ii;
 142                 int jj;
 143                 device_t dev;
 144                 struct resource *res;
 145                 switch(sysconf.hcid[i]) {
 146                 case 1:
 147                 case 3:
 148                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 149                         if (dev) {
 150                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 151                                 if (res) {
 152                                         for(jj=0; jj<4; jj++) {
 153                                                 //Slot 1 PCI-X 133/100/66
 154                                                 for(ii=0;ii<4;ii++) {
 155                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
 156                                                 }
 157                                         }
 158                                 }
 159                         }
 160
 161                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 162                         if (dev) {
 163                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 164                                 if (res) {
 165                                         for(jj=0; jj<4; jj++) {
 166                                                 //Slot 2 PCI-X 133/100/66
 167                                                 for(ii=0;ii<4;ii++) {
 168                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
 169                                                 }
 170                                         }
 171                                 }
 172                         }
 173
 174                         break;
 175                 case 2:
 176
 177                 //  Slot AGP
 178                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 179                         break;
 180                 }
 181
 182                 j++;
 183          }
 184
 185
 186
 187         /* Local Ints:  Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 188         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 189         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 190         /* There is no extension information... */
 191
 192         /* Compute the checksums */
 193         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 194         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 195         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 196                 mc, smp_next_mpe_entry(mc));
 197         return smp_next_mpe_entry(mc);
 198 }
 199
 200 unsigned long write_smp_table(unsigned long addr)
 201 {
 202         void *v;
 203         v = smp_write_floating_table(addr);
 204         return (unsigned long)smp_write_config_table(v);
 205 }