2 # This file is part of the coreboot project.
4 # Copyright (C) 2007 Advanced Micro Devices, Inc.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; version 2 of the License.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program; if not, write to the Free Software
17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 uses USE_FALLBACK_IMAGE
27 uses USE_FAILOVER_IMAGE
28 uses HAVE_FALLBACK_BOOT
29 uses HAVE_FAILOVER_BOOT
32 uses HAVE_OPTION_TABLE
34 uses CONFIG_MAX_PHYSICAL_CPUS
35 uses CONFIG_LOGICAL_CPUS
44 uses ROM_SECTION_OFFSET
45 uses CONFIG_ROM_PAYLOAD
46 uses CONFIG_ROM_PAYLOAD_START
47 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
48 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
56 uses LB_CKS_RANGE_START
59 uses MAINBOARD_PART_NUMBER
62 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
63 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
64 uses COREBOOT_EXTRA_VERSION
69 uses DEFAULT_CONSOLE_LOGLEVEL
70 uses MAXIMUM_CONSOLE_LOGLEVEL
71 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
72 uses CONFIG_CONSOLE_SERIAL8250
80 uses CONFIG_CONSOLE_VGA
81 uses CONFIG_PCI_ROM_RUN
82 uses HW_MEM_HOLE_SIZEK
83 uses HW_MEM_HOLE_SIZE_AUTO_INC
85 uses HT_CHAIN_UNITID_BASE
86 uses HT_CHAIN_END_UNITID_BASE
87 uses SB_HT_CHAIN_ON_BUS0
88 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
93 uses DCACHE_RAM_GLOBAL_VAR_SIZE
98 uses ENABLE_APIC_EXT_ID
100 uses LIFT_BSP_APIC_ID
102 uses CONFIG_PCI_64BIT_PREF_MEM
104 uses CONFIG_LB_MEM_TOPK
106 uses PCI_BUS_SEGN_BITS
108 uses CONFIG_AP_CODE_IN_CAR
112 uses WAIT_BEFORE_CPUS_INIT
116 uses CONFIG_USE_PRINTK_IN_CAR
118 uses AMD_UCODE_PATCH_FILE
125 ## ROM_SIZE is the size of boot ROM that this board will use.
127 default ROM_SIZE=524288
131 #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
133 #default FALLBACK_SIZE=131072
134 #default FALLBACK_SIZE=0x40000
137 default FALLBACK_SIZE=0x7f000
139 default FAILOVER_SIZE=0x02000
142 #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
143 default CONFIG_LB_MEM_TOPK=16384
146 ## Build code for the fallback boot
148 default HAVE_FALLBACK_BOOT=1
149 default HAVE_FAILOVER_BOOT=1
152 ## Build code to reset the motherboard from coreboot
154 default HAVE_HARD_RESET=1
157 ## Build code to export a programmable irq routing table
159 default HAVE_PIRQ_TABLE=1
160 default IRQ_SLOT_COUNT=11
163 ## Build code to export an x86 MP table
164 ## Useful for specifying IRQ routing values
166 default HAVE_MP_TABLE=1
168 ## ACPI tables will be included
169 default HAVE_ACPI_TABLES=1
171 default ACPI_SSDTX_NUM=31
174 ## Build code to export a CMOS option table
176 default HAVE_OPTION_TABLE=1
179 ## Move the default coreboot cmos range off of AMD RTC registers
181 default LB_CKS_RANGE_START=49
182 default LB_CKS_RANGE_END=122
183 default LB_CKS_LOC=123
186 ## Build code for SMP support
189 default CONFIG_MAX_PHYSICAL_CPUS=8
190 default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
191 default CONFIG_LOGICAL_CPUS=1
193 #default SERIAL_CPU_INIT=0
195 default ENABLE_APIC_EXT_ID=1
196 default APIC_ID_OFFSET=0x00
197 default LIFT_BSP_APIC_ID=1
199 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
201 #default HW_MEM_HOLE_SIZEK=0x200000
203 default HW_MEM_HOLE_SIZEK=0x100000
205 #default HW_MEM_HOLE_SIZEK=0x80000
207 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
208 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
211 default CONFIG_CONSOLE_VGA=1
212 default CONFIG_PCI_ROM_RUN=1
214 #HT Unit ID offset, default is 1, the typical one
215 default HT_CHAIN_UNITID_BASE=0xa
217 #real SB Unit ID, default is 0x20, mean dont touch it at last
218 default HT_CHAIN_END_UNITID_BASE=0x6
220 #make the SB HT chain on bus 0, default is not (0)
221 default SB_HT_CHAIN_ON_BUS0=2
223 #only offset for SB chain?, default is yes(1)
224 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
226 #allow capable device use that above 4G
227 #default CONFIG_PCI_64BIT_PREF_MEM=1
229 #it only be 0, 1, 2, 3, 4 and default is 0
230 #default PCI_BUS_SEGN_BITS=3
233 ## enable CACHE_AS_RAM specifics
235 default USE_DCACHE_RAM=1
236 default DCACHE_RAM_BASE=0xc4000
237 default DCACHE_RAM_SIZE=0x0c000
238 #default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
239 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
240 default CONFIG_USE_INIT=0
242 #default CONFIG_AP_CODE_IN_CAR=1
243 default MEM_TRAIN_SEQ=2
244 default WAIT_BEFORE_CPUS_INIT=0
246 default CONFIG_AMDMCT = 1
249 ## Build code to setup a generic IOAPIC
251 default CONFIG_IOAPIC=1
254 ## Clean up the motherboard id strings
256 default MAINBOARD_PART_NUMBER="Cheetah Fam10"
257 default MAINBOARD_VENDOR="AMD"
258 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
259 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
262 ## Set microcode patch file name
264 ## Barcelona rev Ax: "mc_patch_01000020.h"
265 ## Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
266 ## Barcelona rev B2, B3: "mc_patch_01000083.h"
268 default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
271 ### coreboot layout values
274 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
275 default ROM_IMAGE_SIZE = 65536
278 ## Use a small 8K stack
280 default STACK_SIZE=0x2000
283 ## Use a small 768k heap
285 default HEAP_SIZE=0xc0000
288 ## Only use the option table in a normal image
290 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
293 ## Coreboot C code runs at this location in RAM
295 default _RAMBASE=0x00200000
298 ## Load the payload from the ROM
300 default CONFIG_ROM_PAYLOAD = 1
303 ### Defaults of options that you may want to override in the target config file
307 ## The default compiler
309 default CC="$(CROSS_COMPILE)gcc -m32"
313 ## Disable the gdb stub by default
315 default CONFIG_GDB_STUB=0
318 ## The Serial Console
321 default CONFIG_USE_PRINTK_IN_CAR=1
323 # To Enable the Serial Console
324 default CONFIG_CONSOLE_SERIAL8250=1
326 ## Select the serial console baud rate
327 default TTYS0_BAUD=115200
328 #default TTYS0_BAUD=57600
329 #default TTYS0_BAUD=38400
330 #default TTYS0_BAUD=19200
331 #default TTYS0_BAUD=9600
332 #default TTYS0_BAUD=4800
333 #default TTYS0_BAUD=2400
334 #default TTYS0_BAUD=1200
336 # Select the serial console base port
337 default TTYS0_BASE=0x3f8
339 # Select the serial protocol
340 # This defaults to 8 data bits, 1 stop bit, and no parity
341 default TTYS0_LCS=0x3
344 ### Select the coreboot loglevel
346 ## EMERG 1 system is unusable
347 ## ALERT 2 action must be taken immediately
348 ## CRIT 3 critical conditions
349 ## ERR 4 error conditions
350 ## WARNING 5 warning conditions
351 ## NOTICE 6 normal but significant condition
352 ## INFO 7 informational
353 ## DEBUG 8 debug-level messages
354 ## SPEW 9 Way too many details
356 ## Request this level of debugging output
357 default DEFAULT_CONSOLE_LOGLEVEL=8
358 ## At a maximum only compile in this level of debugging
359 default MAXIMUM_CONSOLE_LOGLEVEL=8
362 ## Select power on after power fail setting
363 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
370 default CONFIG_CBFS=0